參數(shù)資料
型號(hào): DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 23/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
119 of 160
The framer also contains a zero destuffer, which is controlled via the CCR2.0 bit. In both ANSI T1.403
and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol
states that no more than five 1’s should be transmitted in a row so that the data does not resemble an
opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS2196
will automatically look for five 1’s in a row, followed by a 0.
If it finds such a pattern, it will
automatically remove the zero. If the zero destuffer sees six or more 1’s in a row followed by a 0, the 0 is
not removed. The CCR2.0 bit should always be set to a 1 when the DS2196 is extracting the FDL. More
on how to use the DS2196 in FDL applications in this legacy support mode is covered in a separate
Application Note.
RFDLA: RECEIVE FDL REGISTER from FRAMER A (Address = 28 Hex)
RFDLB: RECEIVE FDL REGISTER from FRAMER B (Address = C8 Hex)
(MSB)
(LSB)
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
RFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RFDL7
RFDL.7
MSB of the Received FDL Code
RFDL0
RFDL.0
LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
RMTCH1A: RECEIVE FDL MATCH REGISTER 1 FRAMER A
(Address = 29 Hex)
RMTCH2A: RECEIVE FDL MATCH REGISTER 2 FRAMER A
(Address = 2A Hex)
RMTCH1B: RECEIVE FDL MATCH REGISTER 1 FRAMER B
(Address = C9 Hex)
RMTCH2B: RECEIVE FDL MATCH REGISTER 2 FRAMER B
(Address = CA Hex)
(MSB)
(LSB)
RMFDL7
RMFDL6
RMFDL5
RMFDL4
RMFDL3
RMFDL2
RMFDL1
RMFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RMFDL7
RMTCH1A.7
RMTCH2A.7
RMTCH1B.7
RMTCH2B.7
MSB of the FDL Match Code
RMFDL0
RMTCH1A.0
RMTCH2A.0
RMTCH1B.0
RMTCH2B.0
LSB of the FDL Match Code
When the byte in the Receive FDL Register matches either of the two Receive Match Registers
(RMTCH1/RMTCH2), SR2.2 will be set to a 1 and the INT will go active if enabled via IMR2.2.
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