參數(shù)資料
型號: DS2196LN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP100
封裝: LQFP-100
文件頁數(shù): 139/160頁
文件大?。?/td> 559K
代理商: DS2196LN
DS2196
8 of 160
Programmable pattern generator
Three programmable pattern detectors
Patterns from 1 to 8 bits or 16 bits in Length
Programmable On-chip Bit Error Rate Testing
Pseudorandom patterns including QRSS
User defined repetitive patterns
Daly pattern
Error insertion
Bit and error counts
Payload Error Insertion
Error insertion in the payload portion of the T1 frame in the transmit path
Errors can be inserted over the entire frame or selected channels
Insertion options include continuous and absolute number with selectable insertion rates
Function Isolation
All key signals are routed to pins
LIU, Framer A and Framer B can be disconnected from each other
Supports both NRZ and bipolar interfaces
F-Bit corruption for line testing
Programmable output clocks for Fractional T1
Fully independent transmit and receive functionality in each framer
Large path and line error counters including BPV, CV, CRC6, and framing bit errors
Ability to calculate and check CRC6 according to the Japanese standard
Ability to generate Yellow Alarm according to the Japanese standard
Per channel loopback
RCL, RLOS, RRA, and RAIS alarms interrupt on change of state
Hardware pins to indicate receive loss of sync and receive bipolar violations
IEEE 1149.1 JTAG Boundary Scan
相關PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
DS21FF44N DATACOM, FRAMER, PBGA300
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
相關代理商/技術參數(shù)
參數(shù)描述
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