參數(shù)資料
型號： DS2196LN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP100
封裝： LQFP-100
文件頁數(shù)： 25/160頁
文件大?。?/td> 559K
代理商： DS2196LN
DS2196
120 of 160
18.2.3 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full 8 bits has been shifted out, the framer will signal the host microcontroller
that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The INT will also
toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new value. If the TFDL
is not updated, the old value in the TFDL will be transmitted once again. The framer also contains a zero
stuffer, which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016, communications on
the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than five 1’s
should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110)
or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically look for five 1’s in a
row. If it finds such a pattern, it will automatically insert a 0 after the five 1’s. The CCR2.0 bit should
always be set to a 1 when the framer is inserting the FDL. More on how to use the DS2196 in FDL
applications is covered in a separate Application Note.
TFDLA: TRANSMIT FDL REGISTER for FORMATTER A (Address = 7E Hex)
TFDLB: TRANSMIT FDL REGISTER for FORMATTER B (Address = FE Hex)
[Also used to insert Fs framing pattern in D4 framing mode; see Section 18.3]
(MSB)
(LSB)
TFDL7
TFDL6
TFDL5
TFDL4
TFDL3
TFDL2
TFDL1
TFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
TFDL7
TFDL.7
MSB of the FDL code to be transmitted
TFDL0
TFDL.0
LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
18.3 D4/SLC–96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the
device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to
1Ch and the following bits must be programmed as shown: TCR1.2=0 (source Fs data from the TFDL
register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries)
Since the SLC–96 message fields share the Fs–bit position, the user can access the message fields via the
TFDL and RFDL registers. Please see the separate Application Note for a detailed description of how to
implement a SLC–96 function.
相關(guān)PDF資料
PDF描述
DS21FF44 DATACOM, FRAMER, PBGA300
DS21FF44N DATACOM, FRAMER, PBGA300
DS21FT40N DATACOM, FRAMER, PBGA300
DS21FT40 DATACOM, FRAMER, PBGA300
DS21FT42 DATACOM, FRAMER, PBGA300
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2196LN+ 功能描述:網(wǎng)絡控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS219T 功能描述:烙鐵 DESOLDERING HEAD RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included
DS21E352 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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DS21E354 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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