參數(shù)資料
型號(hào): DS21Q44T+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 27/105頁(yè)
文件大?。?/td> 0K
描述: IC FRAMER ENHANCED E1 4X 128TQFP
標(biāo)準(zhǔn)包裝: 72
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q44
28 of 105
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RBCS
RESE
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa8S
RCR2.7
Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit
position; set to zero to force RLCLK low during Sa8 bit
position. See Section 18 for timing details.
Sa7S
RCR2.6
Sa7 Bit Select. Set to one to have RLCLK pulse at the Sa7 bit
position; set to zero to force RLCLK low during Sa7 bit
position. See Section 18 for timing details.
Sa6S
RCR2.5
Sa6 Bit Select. Set to one to have RLCLK pulse at the Sa6 bit
position; set to zero to force RLCLK low during Sa6 bit
position. See Section 18 for timing details.
Sa5S
RCR2.4
Sa5 Bit Select. Set to one to have RLCLK pulse at the Sa5 bit
position; set to zero to force RLCLK low during Sa5 bit
position. See Section 18 for timing details.
Sa4S
RCR2.3
Sa4 Bit Select. Set to one to have RLCLK pulse at the Sa4 bit
position; set to zero to force RLCLK low during Sa4 bit
position. See Section 18 for timing details.
RBCS
RCR2.2
Receive Side Backplane Clock Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
RESE
RCR2.1
Receive Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
RCR2.0
Not Assigned. Should be set to zero when written.
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB)
(LSB)
ODF
TFPT
T16S
TUA1
TSiS
TSA1
TSM
TSIO
SYMBOL
POSITION
NAME AND DESCRIPTION
ODF
TCR1.7
Output Data Format.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG=0
TFPT
TCR1.6
Transmit Timeslot 0 Pass Through.
0 = FAS bits/Sa bits/Remote Alarm sourced internally from the
TAF and TNAF registers
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
T16S
TCR1.5
Transmit Timeslot 16 Data Select.
0 = sample timeslot 16 at TSER pin
1 = source timeslot 16 from TS0 to TS15 registers
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