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參數(shù)資料
| 型號： | DS21Q44T+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 57/105頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER ENHANCED E1 4X 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 72 |
| 控制器類型： | E1 調(diào)幀器 |
| 接口： | 并行/串行 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 75mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x20） |
| 包裝： | 管件 |
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DS21Q44
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Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset
(CCR6.0 & CCR6.1) function forces the elastic stores to a depth of one frame unconditionally. Data is
lost during the reset. The second method, the Elastic Store Align ( CCR5.5 & CCR5.6) forces the elastic
store depth to a minimum depth of half a frame only if the current pointer separation is already less then
half a frame. If a realignment occurs data is lost. In both mechanisms, independent resets are provided
for both the receive and transmit elastic stores.
13.1 Receive Side
If the receive side elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz
(RCR2.2 =0) or 2.048 MHz (RCR2.2=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR1.5=1) or having the RSYNC pin provide a
pulse on frame/multiframe boundaries (RCR1.5=0). If the user wishes to obtain pulses at the frame
boundary, then RCR1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe
boundary, then RCR1.6 must be set to one. The DS21Q44 will always indicate frame boundaries via the
RFSYNC output whether the elastic store is enabled or not. If the elastic store is enabled, then either
CAS (RCR1.7=0) or CRC4 (RCR1.7=1) multiframe boundaries will be indicated via the RMSYNC
output. If the user selects to apply a 1.544 MHz clock to the RSYSCLK pin, then every fourth channel of
the received E1 data will be deleted and a F–bit position (which will be forced to one) will be inserted.
Hence Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted
from the received E1 data stream. Also, in 1.544 MHz applications, the RCHBLK output will not be
active in Channels 25 through 32 (or in other words, RCBR4 is not active). See Section 18 for timing
details. If the 512–bit elastic buffer either fills or empties, a controlled slip will occur. If the buffer
empties, then a full frame of data (256 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will
be set to a one. If the buffer fills, then a full frame of data will be deleted and the SR1.4 and RIR.4 bits
will be set to a one.
13.2 Transmit Side
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR3.7. A 1.544 MHz (CCR3.1=0) or 2.048 MHz (CCR3.1=1) clock can be applied
to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192 MHz. If the user
selects to apply a 1.544 MHz clock to the TSYSCLK pin, then the data sampled at TSER will be ignored
every fourth channel. Hence Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and
28) will be ignored. The user must supply a 8-kHz frame sync pulse to the TSSYNC input. See Section
18 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0 bit and the
direction of the slip is reported in the RIR.6 and RIR.7 bits.
14. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
Each framer in the DS21Q44 provides for access to both the Sa and the Si bits via three different
methods. The first is via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The
first method is discussed in Section 14.1. The second involves using the internal RAF/RNAF and
TAF/TNAF registers and is discussed in Section 14.2 The third method which is covered in Section 14.3
involves an expanded version of the second method and is one of the features added to the DS21Q44
from the original DS21Q43 definition.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q44T+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q44TN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48A3N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V Quad E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21Q48B | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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