參數(shù)資料
型號: DS21Q44T+
廠商: Maxim Integrated Products
文件頁數(shù): 31/105頁
文件大?。?/td> 0K
描述: IC FRAMER ENHANCED E1 4X 128TQFP
標(biāo)準(zhǔn)包裝: 72
控制器類型: E1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-LQFP(14x20)
包裝: 管件
DS21Q44
31 of 105
FRAMER LOOPBACK
When CCR1.7 is set to a one, the framer will enter a Framer LoopBack (FLB) mode. See Figure 1–1 for
more details. This loopback is useful in testing and debugging applications. In FLB, the framer will loop
data from the transmit side back to the receive side. When FLB is enabled, the following will occur:
1) Data will be transmitted as normal at TPOS and TNEG.
2) Data input via RPOS and RNEG will be ignored.
3) The RCLK output will be replaced with the TCLK input.
CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)
(MSB)
(LSB)
ECUS
VCRFS
AAIS
ARA
RSERC
LOTCMC
RFF
RFE
SYMBOL
POSITION
NAME AND DESCRIPTION
ECUS
CCR2.7
Error Counter Update Select. See Section 8 for details.
0=update error counters once a second
1=update error counters every 62.5 ms (500 frames)
VCRFS
CCR2.6
VCR Function Select. See Section 8 for details.
0=count BiPolar Violations (BPVs)
1=count Code Violations (CVs)
AAIS
CCR2.5
Automatic AIS Generation.
0=disabled
1=enabled
ARA
CCR2.4
Automatic Remote Alarm Generation.
0=disabled
1=enabled
RSERC
CCR2.3
RSER Control.
0=allow RSER to output data as received under all conditions
1=force RSER to one under loss of frame alignment conditions
LOTCMC
CCR2.2
Loss of Transmit Clock Mux Control. Determines whether
the transmit side formatter should switch to the ever present
RCLK if the TCLK should fail to transition (see Figure 1–1).
0=do not switch to RCLK if TCLK stops
1=switch to RCLK if TCLK stops
RFF
CCR2.1
Receive Force Freeze. Freezes receive side signaling at RSIG
(and RSER if CCR3.3=1); will override Receive Freeze Enable
(RFE). See Section 10 or details.
0=do not force a freeze event
1=force a freeze event
RFE
CCR2.0
Receive Freeze Enable. See Section 10 for details.
0=no freezing of receive signaling data will occur
1=allow freezing of receive signaling data at RSIG (and RSER
if CCR3.3=1).
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