參數(shù)資料
型號： DS21Q44T+
廠商： Maxim Integrated Products
文件頁數(shù)： 60/105頁
文件大?。?/td> 0K
描述： IC FRAMER ENHANCED E1 4X 128TQFP
標準包裝： 72
控制器類型： E1 調(diào)幀器
接口： 并行/串行
電源電壓： 2.97 V ~ 3.63 V
電流 - 電源： 75mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應商設備封裝： 128-LQFP（14x20）
包裝： 管件
DS21Q44
58 of 105
TNAF: TRANSMIT NONALIGN FRAME REGISTER (Address=21 Hex)
(MSB)
(LSB)
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
[Bit 2 must be programmed to one; the DS21Q44 does not automatically set this bit]
SYMBOL
POSITION
NAME AND DESCRIPTION
Si
TNAF.7
International Bit.
1
TNAF.6
Frame Non–Alignment Signal Bit.
A
TNAF.5
Remote Alarm (used to transmit the alarm).
Sa4
TNAF.4
Additional Bit 4.
Sa5
TNAF.3
Additional Bit 5.
Sa6
TNAF.2
Additional Bit 6.
Sa7
TNAF.1
Additional Bit 7.
Sa8
TNAF.0
Additional Bit 8.
14.3 Internal Register Scheme Based on CRC4 Multiframe
On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the
Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4
Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these
registers. The user has 2 ms to retrieve the data before it is lost. The MSB of each register is the first
received. Please see the register descriptions below and the Transmit Data Flow diagram in Section 18
for more details. On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4
to TSa8) that via the Transmit Sa Bit Control Register (TSaCR), can be programmed to insert both Si and
Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status
Register 2 (SR2.5). The host can use the SR2.5 bit to know when to update these registers. It has 2 ms to
update the data or else the old data will be retransmitted. The MSB of each register is the first bit
transmitted. Please see the register descriptions below and the Transmit Data Flow diagram in Section 18
for more details.
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