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參數(shù)資料
| 型號(hào)： | DS21Q59LN+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 36/76頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX E1 QUAD 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類(lèi)型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 4/4 |
| 規(guī)程： | E1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤(pán) |
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DS21Q59 Quad E1 Transceiver
41 of 76
15.
TRANSMIT CLOCK SOURCE
Depending on the DS21Q59’s operating mode, the transmit clock can be derived from different sources. In a basic
configuration, where the IBO function is disabled, the transmit clock is normally sourced from the TCLK pin. In this
mode, a 2.048MHz clock with ±50ppm accuracy is applied to the TCLK pin. If the signal at TCLK is lost, the
DS21Q59 automatically switches to either the system reference clock present on the REFCLK pin or to the
recovered clock off the same port, depending on which source the host assigned as the backup clock. At the same
time the host can be notified of the loss-of-transmit clock through an interrupt. The host can at any time force a
switchover to one of the two backup clock sources regardless of the state of the TCLK pin.
When the IBO function is enabled, the transmit clock must be synchronous to the system clock since slips are not
allowed in the transmit direction. In this mode, the TCLK pin is ignored, and a transmit clock is automatically
provided by the IBO circuit by dividing the clock present on the SYSCLK pin by 2, 4, or 8. In this configuration, if the
signal present on the SYSCLK pin is lost, the DS21Q59 automatically switches to either the system reference clock
or to the recovered clock off the same port, depending on which source the host assigned as the backup clock. The
host can at any time force a switchover to one of the two backup clock sources regardless of the state of the
SYSCLK pin.
16.
IDLE CODE INSERTION
The transmit idle registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten with the code
placed in the transmit idle definition register (TIDR). This allows the same 8-bit code to be placed into any of the 32
E1 channels. Each of the bit positions in the transmit idle registers represents a DS0 channel in the outgoing frame.
When these bits are set to 1, the corresponding channel transmits the idle code contained in the TIDR.
Register Name:
TIR1, TIR2, TIR3, TIR4
Register Description:
Transmit Idle Registers
Register Address:
24 Hex, 25 Hex, 26 Hex, 27 Hex
Bit #
7
6
5
4
3
2
1
0
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
Name
CH32
CH31
CH30
CH29
CH26
CH25
NAME
BIT
FUNCTION
CH1 to CH32
TIR1.0 to 4.7
Transmit Idle Code-Insertion Control Bits
0 = do not insert the idle code in the TIDR into this channel
1 = insert the idle code in the TIDR into this channel
Register Name:
TIDR
Register Description:
Transmit Idle Definition Register
Register Address:
23 Hex
Bit #
7
6
5
4
3
2
1
0
Name
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
NAME
BIT
FUNCTION
TIDR7
7
MSB of the Idle Code (This bit is transmitted first.)
TIDR6
6
—
TIDR5
5
—
TIDR4
4
—
TIDR3
3
—
TIDR2
2
—
TIDR1
1
—
TIDR0
0
LSB of the Idle Code (This bit is transmitted last.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21Q59LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21S07A | 制造商:Maxim Integrated Products 功能描述: |
| DS21S07AE | 功能描述:SCSI 接口集成電路 RoHS:否 制造商:Texas Instruments 工作電源電壓:2.7 V to 5.25 V 電源電流:13 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SSOP-36 封裝:Tube |
| DS21S07AE/T | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:SCSI Terminator |
| DS21S07AE/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: 制造商:Maxim Integrated Products 功能描述:IC TERMINATOR SCSI 20-TSSOP |
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