參數(shù)資料
型號: DS21Q59LN+
廠商: Maxim Integrated Products
文件頁數(shù): 60/76頁
文件大?。?/td> 0K
描述: IC TXRX E1 QUAD 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 4/4
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
DS21Q59 Quad E1 Transceiver
63 of 76
26.
AC TIMING PARAMETERS AND DIAGRAMS
26.1 Multiplexed Bus AC Characteristics
Table 26-A. AC Characteristics—Multiplexed Parallel Port
(VDD = 3.3V
±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.)
(Figure 26-1, Figure 26-2, and Figure 26-3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Cycle Time
tCYC
200
ns
Pulse Width, DS Low or
RD High
PWEL
100
ns
Pulse Width, DS High or
RD Low
PWEH
100
ns
Input Rise/Fall times
tR, tF
20
ns
R/
W Hold Time
tRWH
10
ns
R/
W Setup Time Before DS High
tRWS
50
ns
CS Setup Time Before DS, WR, or
RD Active
tCS
20
ns
CS Hold Time
tCH
0
ns
Read Data Hold Time
tDHR
10
50
ns
Write Data Hold Time
tDHW
0
ns
Muxed Address Valid to AS or ALE
Fall
tASL
15
ns
Muxed Address Hold Time
tAHL
10
ns
Delay Time DS,
WR, or RD to AS or
ALE Rise
tASD
20
ns
Pulse Width AS or ALE High
PWASH
30
ns
Delay Time, AS or ALE to DS,
WR,
or
RD
tASED
10
ns
Output Data-Delay Time from DS or
RD
tDDR
20
140
ns
Data Setup Time
tDSW
50
ns
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