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| 型號(hào)： | DS31412N |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 15/89頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 12CH DS3/3 FRAMER 349-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 960mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 349-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 349-HCBGA（27x27） |
| 包裝： | 托盤 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
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7.6 Common and Line Interface Registers
This section describes the registers responsible for top-level configuration, control, and status of each framer,
including resets, clocks, pin controls, and line interface functions.
Table 7-C. Common Line Interface Register Map
ADDR
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00h
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
01h
LOTCMC
ZCSD
BIN
MECU
AECU
TUA1
DISABLE
RST
02h
OSTCS
TCCLK
N/A
RZSF
N/A
DLB
LLB
PLB
03h
TDENMS
TSOFC
TOHENI
TOHI
TSOFI
TICLKI
TDATI
TDENI
04h
RDENMS
ROOFI
RLOSI
RDATH
RSOFI
ROCLKI
RDATI
RDENI
05h
RNEGI
RPOSI
RCLKI
TNEGH
TPOSH
TNEGI
TPOSI
TCLKI
06h
INT8
INT7
INT6
INT5
INT4
INT3
INT2
INT1
07h
N/A
INT12
INT11
INT10
INT9
08h
LORC
LOTC
T3E3
FEAC
HDLC
BERT
COVF
N/A
09h
LORCL
LOTCL
N/A
COVFL
OSTL
0Ah
LORCIE
LOTCIE
T3E3IE
FEACIE
HDLCIE
BERTIE
COVFIE
OSTIE
Register Name:
ID
Register Description:
ID Register
Register Address:
00h
Bit #
7
6
5
4
3
2
1
0
Name
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Default
—
This register is a global resource and is mapped into address 00h in every framer in the device.
Bits 0 to 7: Device ID (ID[7:0]). Read-only. Contact the factory for details on the meaning of the ID bits.
Register Name:
MC1
Register Description:
Master Configuration Register 1
Register Address:
01h
Bit #
7
6
5
4
3
2
1
0
Name
LOTCMC
ZCSD
BIN
MECU
AECU
TUA1
DISABLE
RST
Default
0
1
0
Bit 0: Framer Reset (RST). When this bit is set to logic 1, it forces all of the internal registers in the framer (except
this RST bit) to their default state. Only the framer associated with this register is reset. RST must be high for a
minimum of 100ns and then returned low. This register bit is logically ORed with the
RST pin.
0 = normal operation
1 = force all internal registers to their default values
Bit 1: Framer Disable (DISABLE). Setting this bit disables the framer by stopping all clocks. This reduces the
power the framer requires. After the framer is enabled again by clearing this bit, the RST bit must be toggled to
initialize the framer again. Toggling the RST bit when DISABLE = 1 automatically enables the framer again.
0 = enable framer
1 = disable framer
Bit 2: Transmit Unframed All Ones (TUA1). Enables the transmission of an unframed all-ones pattern on
TPOS/TNEG or TNRZ. This pattern is sometimes called physical AIS.
0 = disable transmission of unframed all ones
1 = enable transmission of unframed all ones (reset default value)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS31415 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
| DS31415_1107 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
| DS31415DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS31415 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31415GN+ | 制造商:Microsemi Corporation 功能描述:SINGLE DPLL TIMING IC W/APLL & 1588 CLOCK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:SINGLE DPLL TIMING IC W/APLL & 1588 CLOCK - Rail/Tube 制造商:Microsemi 功能描述:DPLL 256-Pin CSBGA |
| DS3141N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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