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參數(shù)資料
| 型號： | DS31412N |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 18/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 12CH DS3/3 FRAMER 349-BGA |
| 標準包裝： | 1 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 960mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 349-BGA 裸露焊盤 |
| 供應商設備封裝： | 349-HCBGA（27x27） |
| 包裝： | 托盤 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
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Register Name:
MC3
Register Description:
Master Configuration Register 3
Register Address:
03h
Bit #
7
6
5
4
3
2
1
0
Name
TDENMS
TSOFC
TOHENI
TOHI
TSOFI
TICLKI
TDATI
TDENI
Default
0
Bit 0: TDEN Invert Enable (TDENI)
0 = do not invert the TDEN/TGCLK signal (normal mode)
1 = invert the TDEN/TGCLK signal (inverted mode)
Bit 1: TDAT Invert Enable (TDATI)
0 = do not invert the TDAT signal (normal mode)
1 = invert the TDAT signal (inverted mode)
Bit 2: TICLK Invert Enable (TICLKI)
0 = do not invert the TICLK signal (normal mode)
1 = invert the TICLK signal (inverted mode)
Bit 3: TSOF Invert Enable (TSOFI)
0 = do not invert the TSOF signal (normal mode)
1 = invert the TSOF signal (inverted mode)
Bit 4: TOH Invert Enable (TOHI)
0 = do not invert the TOH signal (normal mode)
1 = invert the TOH signal (inverted mode)
Bit 5: TOHEN Invert Enable (TOHENI)
0 = do not invert the TOHEN signal (normal mode)
1 = invert the TOHEN signal (inverted mode)
Bit 6: Transmit Start-of-Frame I/O Control (TSOFC). When this bit is logic 1, the TSOF pin is an output and
pulses for the last TICLK cycle of each frame. When this bit is 0, the TSOF pin is an input, and the device uses it to
determine the frame boundaries. See Figure 5-1 for functional timing information.
0 = TSOF is an input (reset default as input)
1 = TSOF is an output
Bit 7: Transmit Data-Enable Mode Select (TDENMS). When this bit is logic 0, the TDEN/TGCLK output has the
TDEN (data enable) function. TDEN asserts during payload bit times and de-asserts during overhead bit times.
When this bit is logic 1, TDEN/TGCLK has the TGCLK (gapped clock) function. TGCLK pulses during payload bit
times and is suppressed during overhead bit times. The TCCLK control bit in the MC2 register has precedence
over this control bit. See Figure 5-1 for functional timing information.
0 = TDEN (data enable) mode
1 = TGCLK (gapped clock) mode
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS31415 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
| DS31415_1107 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3-Input, 4-Output, Single DPLL Timing IC with Sub-ps Output Jitter and 1588 Clock |
| DS31415DK | 功能描述:網(wǎng)絡開發(fā)工具 DS31415 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| DS31415GN+ | 制造商:Microsemi Corporation 功能描述:SINGLE DPLL TIMING IC W/APLL & 1588 CLOCK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:SINGLE DPLL TIMING IC W/APLL & 1588 CLOCK - Rail/Tube 制造商:Microsemi 功能描述:DPLL 256-Pin CSBGA |
| DS3141N | 功能描述:網(wǎng)絡控制器與處理器 IC Single DS3/E3 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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