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參數(shù)資料
| 型號(hào)： | DS31412N |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 59/89頁 |
| 文件大小： | 0K |
| 描述： | IC 12CH DS3/3 FRAMER 349-BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 控制器類型： | DS3/E3 調(diào)幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 960mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 349-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 349-HCBGA（27x27） |
| 包裝： | 托盤 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
62 of 89
Register Name:
RHDLC1
Register Description:
Receive HDLC FIFO Data
Register Address:
5Ch
Bit #
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
—
Note: After the RHDLC2 register is read, the receive FIFO read pointer advances and both the RHDLC1 and RHDLC2 registers are updated
with the next data/status from the receive FIFO. The host processor should read RHDLC1 first to retrieve the FIFO data and then immediately
read RHDLC2 to retrieve the associated FIFO status bits.
Bits 0 to 7: Receive FIFO Data (D[7:0]). These bits contain the next byte of receive FIFO data. D0 is the LSB and
is the first bit received by the framer, while D7 is the MSB and is the last bit received. Reading this register does
not cause the receive FIFO read pointer to advance.
Register Name:
RHDLC2
Register Description:
Receive HDLC FIFO Status
Register Address:
5Dh
Bit #
7
6
5
4
3
2
1
0
Name
N/A
PS1
PS0
CBYTE
OBYTE
Default
—
Bit 0: Opening Byte Indicator (OBYTE). This bit is set to 1 when the RHDLC1 register contains the first byte of an
HDLC packet.
Bit 1: Closing Byte Indicator (CBYTE). This bit is set to 1 when the RHDLC1 register contains the last byte of an
HDLC packet, whether the packet is valid or not. The host processor can check the PS[1:0] bits to determine
packet validity.
Bits 2, 3: Packet Status (PS[1:0]). These bits are only valid when the CBYTE bit is set to 1. These bits indicate
the validity of the incoming packet and the cause of the problem if the packet was received in error.
PS[1:0]
PACKET STATUS
REASON FOR INVALID RECEPTION OF THE PACKET
00
Valid
—
01
Invalid
Corrupt CRC
10
Invalid
Incoming packet was either too short (less than 4 bytes including the CRC)
or did not contain an integral number of octets
11
Invalid
Abort sequence detected
Packets fewer than four bytes long (including the FCS) are invalid and the data that appears in the FIFO in such
instances is meaningless. If only one byte is received between flags, then both the CBYTE and OBYTE bits are
set. If two bytes are received, then OBYTE is set for the first byte received and CBYTE is set for the second byte
received. If three bytes are received, then OBYTE is set for the first byte received and CBYTE is set for the third
byte received. In all of these cases, the packet status is reported as PS[1:0] = 10, and the data in the FIFO should
be ignored.
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