參數(shù)資料
型號(hào)： DS3148N
廠商： Maxim Integrated Products
文件頁數(shù)： 16/89頁
文件大小： 0K
描述： IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 640mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
23 of 89
Bit 3: Automatic Error-Counters Update Defeat (AECU). When this bit is logic 0, the device automatically
updates the DS3/E3 performance error counters on an internally created 1-second boundary based on the RCLK
or TCLK signal, depending on the OSTCS control bit. The host processor is notified of the update through the
setting of the OST status bit in the MSRL register. In this mode, the host processor has a full 1-second period to
retrieve the error count information before it is overwritten with the next update. When this bit is set high, the device
disables the automatic 1-second update and enables a manual update mode. In the manual update mode, the
device relies on either the RECU hardware input signal or the MECU control bit to update the error counters. The
RECU hardware input signal and MECU control bit are logically ORed and therefore a 0-to-1 transition on either
initiates an error counter update. After either the RECU signal or MECU bit has toggled, the host processor must
wait at least 100ns before reading the error counters to allow the device time to complete the update.
0 = enable the automatic update mode and disable the manual update mode
1 = disable the automatic update mode and enable the manual update mode
Bit 4: Manual Error-Counter Update (MECU). A 0-to-1 transition on this bit causes the device to update the
performance error counters. This bit is ignored if the AECU control bit is logic 0. This bit must be cleared and set
again for a subsequent update. This bit is logically ORed with the RECU input pin.
Bit 5: DS3/E3 POS/NEG Binary Mode Select (BIN). Selects the mode of the LIU interface signals.
0 = dual rail mode (data on TPOS/TNEG and RPOS/RNEG)
1 = binary NRZ mode (data on TNRZ and RNRZ with line-code violation pulses on RLCV)
Bit 6: Zero Code Suppression Disable (ZCSD). When BIN = 1, zero code suppression is automatically disabled
and ZCSD has no effect.
0 = enable the B3ZS/HDB3 encoder and decoder; coding is AMI with zero substitution
1 = disable the B3ZS/HDB3 encoder and decoder; coding is AMI without zero substitution
Bit 7: Loss-of-Transmit Clock Mux Control (LOTCMC). The device can detect if the TICLK fails to transition. If
this bit is logic 0, the device takes no action (other than setting the LOTC status bit) when the TICLK fails to
transition. If this bit is logic 1, when TICLK fails to transition the device automatically switches the transmitter to the
input receive clock (RCLK) and transmits AIS.
0 = do not switch the transmitter to RCLK if TICLK fails to transition
1 = automatically switch the transmitter to RCLK and transmit AIS if TICLK fails to transition
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