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參數資料
| 型號： | DS3148N |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 38/89頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 8CH DS3/3 FRAMER 349-BGA |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1 |
| 控制器類型： | DS3/E3 調幀器 |
| 接口： | LIU |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 640mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 349-BGA 裸露焊盤 |
| 供應商設備封裝： | 349-HCBGA（27x27） |
| 包裝： | 托盤 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
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7.8 DS3/E3 Performance Error Counters
There are six internal error counters and six corresponding error count registers in the DS3/E3 framer. All of the
error counters and count registers are 16 bits in length. The framer can be configured to update the count registers
with the latest counter values automatically once a second or manually through either the MECU bit in the MC1
register or the RECU input pin. When the count registers are updated through any of these methods, the internal
error counters are reset to 0. All the error counters saturate when full and do not roll over. When any of the error
counters are saturated, the COVF bit is set in the MSR register.
Register Name:
BPVCR1
Register Description:
Bipolar Violation Count Register 1
Register Address:
20h
Bit #
7
6
5
4
3
2
1
0
Name
BPV7
BPV6
BPV5
BPV4
BPV3
BPV2
BPV1
BPV0
Default
0
Register Name:
BPVCR2
Register Description:
Bipolar Violation Count Register 2
Register Address:
21h
Bit #
7
6
5
4
3
2
1
0
Name
BPV15
BPV14
BPV13
BPV12
BPV11
BPV10
BPV9
BPV8
Default
0
Bits 0 to 15: Bipolar Violation Count (BPV[15:0]). This count register contains the value of the internal BPV/CV
error counter latched during the last error counter update. In DS3 mode, the internal counter counts bipolar
violations (BPV). In the E3 mode, the counter can be configured through the E3CVE bit in the T3E3CR2 register to
count BPVs or code violations (CV). A BPV is defined as consecutive pulses (or marks) of the same polarity that
are not part of a B3ZS/HDB3 codeword. A CV is defined in ITU O.162 as two consecutive BPVs of the same
polarity. When the line interface is in binary mode (BIN = 1 in the MC1 register), the internal counter increments for
each RCLK clock cycle that the RLCV pin is active. The RLCV pin is normally active high but can be inverted using
the RNEGI bit in the MC5 register. The BPV counter ignores the RLCV pin when the device is in diagnostic
loopback (DLB = 1 in register MC2).
Register Name:
EXZCR1
Register Description:
Excessive Zero Count Register 1
Register Address:
22h
Bit #
7
6
5
4
3
2
1
0
Name
EXZ7
EXZ6
EXZ5
EXZ4
EXZ3
EXZ2
EXZ1
EXZ0
Default
0
Register Name:
EXZCR2
Register Description:
Excessive Zero Count Register 2
Register Address:
23h
Bit #
7
6
5
4
3
2
1
0
Name
EXZ15
EXZ14
EXZ13
EXZ12
EXZ11
EXZ10
EXZ9
EXZ8
Default
0
Bits 0 to 15: Excessive Zero Count (EXZ[15:0]). This count register contains the value of the internal EXZ error
counter latched during the last error counter update. The internal counter counts excessive zero occurrences
(EXZ). An EXZ occurrence is defined as three or more consecutive 0s in DS3 mode and four or more consecutive
0s in E3 mode. As an example, a string of eight consecutive 0s is a single EXZ occurrence and would only
increment this counter once.
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