參數(shù)資料
型號： DS3148N
廠商： Maxim Integrated Products
文件頁數(shù)： 19/89頁
文件大?。?/td> 0K
描述： IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 640mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
26 of 89
Register Name:
MC4
Register Description:
Master Configuration Register 4
Register Address:
04h
Bit #
7
6
5
4
3
2
1
0
Name
RDENMS
ROOFI
RLOSI
RDATH
RSOFI
ROCLKI
RDATI
RDENI
Default
0
1
0
Bit 0: RDEN Invert Enable (RDENI)
0 = do not invert the RDEN signal (normal mode)
1 = invert the RDEN signal (inverted mode)
Bit 1: RDAT Invert Enable (RDATI)
0 = do not invert the RDAT signal (normal mode)
1 = invert the RDAT signal (inverted mode)
Bit 2: ROCLK Invert Enable (ROCLKI)
0 = do not invert the ROCLK signal (normal mode)
1 = invert the ROCLK signal (inverted mode)
Bit 3: RSOF Invert Enable (RSOFI)
0 = do not invert the RSOF signal (normal mode)
1 = invert the RSOF signal (inverted mode)
Bit 4: RDAT Force High (RDATH). This bit is set to logic 1 at reset, which puts an all-ones signal on the RDAT
pin. This pin should be cleared once the device has framed to a valid signal. The RDAT pin can be forced low by
setting both the RDATH and RDATI control bits.
0 = do not force RDAT high (normal mode)
1 = force RDAT high (default reset mode)
Bit 5: RLOS Invert Enable (RLOSI)
0 = do not invert the RLOS signal (normal mode)
1 = invert the RLOS signal (inverted mode)
Bit 6: ROOF Invert Enable (ROOFI)
0 = do not invert the ROOF signal (normal mode)
1 = invert the ROOF signal (inverted mode)
Bit 7: Receive Data-Enable Mode Select (RDENMS). When this bit is logic 0, the RDEN/RGCLK output has the
RDEN (data enable) function. RDEN asserts during payload bit times and de-asserts during overhead bit times.
When this bit is logic 1, RDEN/RGCLK has the RGCLK (gapped clock) function. RGCLK pulses during payload bit
times and is suppressed during overhead bit times. See Figure 5-2 for timing information.
0 = RDEN (data enable) mode
1 = RGCLK (gapped clock) mode
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