參數(shù)資料
型號： DS3148N
廠商： Maxim Integrated Products
文件頁數(shù)： 49/89頁
文件大?。?/td> 0K
描述： IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 640mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應商設備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
53 of 89
Register Name:
BBCR1
Register Description:
BERT Bit Counter Register 1 (lower byte)
Register Address:
40h
Bit #
7
6
5
4
3
2
1
0
Name
BBC7
BBC6
BBC5
BBC4
BBC3
BBC2
BBC1
BBC0
Default
0
Register Name:
BBCR2
Register Description:
BERT Bit Counter Register 2
Register Address:
41h
Bit #
7
6
5
4
3
2
1
0
Name
BBC15
BBC14
BBC13
BBC12
BBC11
BBC10
BBC9
BBC8
Default
0
Register Name:
BBCR3
Register Description:
BERT Bit Counter Register 3
Register Address:
42h
Bit #
7
6
5
4
3
2
1
0
Name
BBC23
BBC22
BBC21
BBC20
BBC19
BBC18
BBC17
BBC16
Default
0
Register Name:
BBCR4
Register Description:
BERT Bit Counter Register 4 (upper byte)
Register Address:
43h
Bit #
7
6
5
4
3
2
1
0
Name
BBC31
BBC30
BBC29
BBC28
BBC27
BBC26
BBC25
BBC24
Default
0
Bits 0 to 31: BERT Bit Counter (BBC[31:0]). The BBCR registers are loaded with the value of the internal BERT
bit counter when the LC control bit in the BCR1 register is toggled. This 32-bit counter increments for each data bit
received. The bit counter starts counting when the BERT goes into receive synchronization (SYNC = 1) and
continues counting even if the BERT loses sync. The bit counter saturates and does not roll over. Upon saturation,
the BBCO status bit in the BSR register is set. When the LC bit is toggled, the bit count is loaded into the BBCR
registers and the internal bit counter is cleared. If the BERT is in sync when LC is toggled, the bit counter continues
to count up from zero. If the BERT is out of sync when LC is toggled, the bit counter is held at zero until the BERT
regains sync. The host processor should toggle LC after the BERT has synchronized and then toggle LC again
when the error-checking period is complete. If the framer loses synchronization during this period, then the
counting results are suspect.
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