參數(shù)資料
型號(hào): DS3254DK
廠商: Maxim Integrated Products
文件頁數(shù): 10/71頁
文件大小: 0K
描述: KIT DEMO FOR DS3254
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計(jì)資源: DS3254DK Gerber Files
標(biāo)準(zhǔn)包裝: 1
主要目的: 電信,線路接口單元(LIU)
已用 IC / 零件: DS3254
已供物品: 板,CD
DS3251/DS3252/DS3253/DS3254
18 of 71
Register Name:
RCRn
Register Description:
Receiver Configuration Register
Register Address:
02h, 12h, 22h, 32h
Bit
7
6
5
4
3
2
1
0
Name
ITU
RBIN
RCINV
RJA
RPD
RTS
RMON
RCVUD
Default
0
1
0
Bit 7: ITU CV Mode (ITU). This bit controls what types of bipolar violations (BPVs) are flagged as code violations
on the RLCV pin and counted in the RCV register. It also controls whether or not excessive zero (EXZ) events are
flagged and counted. An EXZ event is the occurrence of a third consecutive zero (DS3 or STS-1 modes) or fourth
consecutive zero (E3 mode) in a sequence of zeros.
0 = In all three modes (DS3, E3, and STS-1) BPVs that are not part of a valid codeword are flagged and
counted. EXZ events are also flagged and counted.
1 = In DS3 and STS-1 modes, BPVs that are not part of valid codewords are flagged and counted. In E3
mode, BPVs that are the same polarity as the last BPV are flagged and counted. EXZ events are not
flagged and counted in any mode.
Bit 6: Receiver Binary Interface Enable (RBIN)
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
disabled.
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations.
The B3ZS/HDB3 encoder is enabled.
Bit 5: Receiver Clock Invert (RCINV)
0 = RPOS/RDAT and RNEG/RLCV are sampled on the falling edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV are sampled on the rising edge of RCLK.
Bit 4: Receiver Jitter Attenuator Enable (RJA). (Note that TCR:TJA = 1 takes precedence over RJA = 1.)
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
Bit 3: Receiver Power-Down Enable (RPD)
0 = enable the receiver
1 = power-down the receiver (RPOS/RDAT, RNEG/RLCV, and RCLK tri-stated)
Bit 2: Receiver Tri-State Enable (RTS). This signal is set to 1 on reset, which tri-states the receiver RPOS/RDAT,
RNEG/RLCV, and RCLK pins. The receiver is left powered up in this mode. The
RTS pin is inverted and logically
ORed with this bit.
0 = enable the receiver outputs
1 = tri-state the receiver outputs (RPOS/RDAT, RNEG/RLCV, and RCLK)
Bit 1: Receiver Monitor Preamp Enable (RMON)
0 = disable the monitor preamp
1 = enable the monitor preamp
Bit 0: Receive Code-Violation Counter Update (RCVUD). When this control bit transitions from low to high, the
RCVL and RCVH registers are loaded with the current code-violation count, and the internal code-violation counter
is cleared.
0
→1 = Update RCV registers and clear internal code-violation counter
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