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| 型號(hào)： | DS3254DK |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 5/71頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEMO FOR DS3254 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 設(shè)計(jì)資源： | DS3254DK Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，線路接口單元（LIU） |
| 已用 IC / 零件： | DS3254 |
| 已供物品： | 板，CD |
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DS3251/DS3252/DS3253/DS3254
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Table 6-E. Parallel Bus Mode Pin Descriptions
Note: These pins are active in parallel bus mode.
NAME
FUNCTION
MOT
I
Motorola-Style Parallel CPU Interface
0 = Parallel CPU interface is Intel-style
1 = Parallel CPU interface is Motorola-style
ALE
I
Address Latch Enable. This signal controls a latch on the A[3:0] inputs. For a nonmultiplexed parallel
CPU interface, ALE is wired high to make the latch transparent. For a multiplexed parallel CPU
interface, the falling edge of ALE latches the address.
CS
I
Chip Select (Active Low).
CS must be asserted to read or write internal registers.
WR / R/W
I
Write Enable (Active Low) or Read/Write Select. For the Intel-style parallel CPU interface (MOT =
0),
WR is asserted to write internal registers. For the Motorola-style parallel CPU interface (MOT = 1),
R/
W determines the type of bus transaction, with R/W = 1 indicating a read and R/W = 0 indicating a
write.
RD / DS
I
Read Enable (Active Low) or Data Strobe (Active Low). For the Intel-style parallel CPU interface
(MOT = 0),
RD is asserted to read internal registers. For the Motorola-style parallel CPU interface
(MOT = 1), the rising edge of
DS writes data to internal registers.
A[5:0]
I
Address Bus. These inputs specify the address of the internal register to be accessed. A5 is not
present on the DS3252. A5 and A4 are not present on the DS3251.
D[7:0]
I/O
Data Bus. These bidirectional lines are inputs during writes to internal registers and outputs during
reads.
INT
O
Interrupt Output (Active Low, Open Drain). This pin is forced low in response to one or more
unmasked, active interrupt sources within the device.
INT remains low until the interrupt is serviced or
masked.
Table 6-F. SPI Bus Mode Pin Descriptions
Note: These pins are active in SPI bus mode.
NAME
FUNCTION
MOT
,
RD, WR
I
Wire these pins low to enable SPI bus mode.
ALE
I
Wire this pin high when using SPI bus mode.
CS
I
Chip Select (Active Low).
CS must be asserted to read or write internal registers.
SCLK
I
Serial Clock for SPI Interface. SCLK is always driven by the SPI bus master.
SDI
I
Serial Data Input for SPI Interface. The SPI bus master transmits data to the device on this pin.
SDO
O
Serial Data Output for SPI Interface
The device transmits data to the SPI bus master on this pin.
CPHA
I
SPI Clock Phase
0 = data is latched on the leading edge of the SCLK pulse
1 = data is latched on the trailing edge of the SCLK pulse
CPOL
I
SPI Clock Polarity
0 = SCLK is normally low and pulses high during bus transactions
1 = SCLK is normally high and pulses low during bus transactions
INT
O
Interrupt Output (Active Low, Open Drain). This pin is forced low in response to one or more
unmasked, active interrupt sources within the device.
INT remains low until the interrupt is serviced or
masked.
Note 1:
PIN TYPES
I = input pin
IPU = input pin with internal 10k pullup
O = output pin
O3 = output pin that can be tri-stated
P = power-supply pin
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參數(shù)描述 |
|---|---|
| DS3254N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254NA3 | 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube |
| DS3256 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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