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| 型號： | DS3254DK |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEMO FOR DS3254 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 設(shè)計資源： | DS3254DK Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 電信，線路接口單元（LIU） |
| 已用 IC / 零件： | DS3254 |
| 已供物品： | 板，CD |
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DS3251/DS3252/DS3253/DS3254
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6. PIN DESCRIPTIONS
Table 6-A through Table 6-C list the pins that are always active. Table 6-D through Table 6-F list the additional pins
that active in each of the three control interface modes. Section 18 shows pin assignments for all three control
interface modes.
Table 6-A. Global Pin Descriptions
Note: These pins are always active.
NAME
FUNCTION
T3MCLK
I/O
T3 Master Clock. If a clock is applied to T3MCLK, it must be transmission-quality (
±20ppm, low jitter).
When present, the T3MCLK signal serves as the DS3 master clock for the CDRs and jitter attenuators
of all LIUs configured for DS3 operation. If T3MCLK is held low, the clock adapter block synthesizes the
DS3 master clock from the clock applied to E3MCLK (first choice) or the clock applied to STMCLK
(second choice). If T3MCLK is held high, each LIU in DS3 mode uses its TCLK signal as its master
clock. If T3MCLK is held low but E3MCLK and STMCLK are not toggling, then each LIU in DS3 mode
uses its TCLK signal as its master clock. Pin is input-only in Hardware mode, input/output in CPU Bus
mode. See Section 12 for more information.
E3MCLK
I/O
E3 Master Clock. If a clock is applied to E3MCLK, it must be transmission-quality (
±20ppm, low jitter).
When present, the E3MCLK signal serves as the E3 master clock for the CDRs and jitter attenuators of
all LIUs configured for E3 operation. If E3MCLK is held low, the clock adapter block synthesizes the E3
master clock from the clock applied to T3MCLK (first choice) or the clock applied to STMCLK (second
choice). If E3MCLK is held high, each LIU in E3 mode uses its TCLK signal as its master clock. If
E3MCLK is held low but T3MCLK and STMCLK are not toggling, then each LIU in E3 mode uses its
TCLK signal as its master clock. Pin is input-only in Hardware mode, input/output in CPU Bus mode.
See Section 12 for more information.
STMCLK
I/O
STS-1 Master Clock. If a clock is applied to STMCLK, it must be transmission-quality (
±20ppm, low
jitter). When present, the STMCLK signal serves as the STS-1 master clock for the CDRs and jitter
attenuators of all LIUs configured for STS-1 operation. If STMCLK is held low, the clock adapter block
synthesizes the STS-1 master clock from the clock applied to T3MCLK (first choice) or the clock
applied to E3MCLK (second choice). If STMCLK is held high, each LIU in STS-1 mode uses its TCLK
signal as its master clock. If STMCLK is held low but T3MCLK and E3MCLK are not toggling, then each
LIU in STS-1 mode uses its TCLK signal as its master clock. Pin is input-only in Hardware mode,
input/output in CPU Bus mode. See Section 12 for more information.
HIZ
IPU
High-Z Enable Input (Active Low, Open Drain, Internal 10k
Pullup to VDD)
0 = tri-state all output pins (Note that the
JTRST pin must be low.)
1 = normal operation
HW
I
Hardware Mode Select
0 = CPU bus mode
1 = Hardware mode
See Section 5 for details.
JTCLK
I
JTAG IEEE 1149.1 Test Serial Clock. JTCLK shifts data into JTDI on the rising edge and out of JTDO
on the falling edge. If boundary scan is not used, JTCLK should be pulled high.
JTDI
IPU
JTAG IEEE 1149.1 Test Serial-Data Input (Internal 10k
Pullup). Test instructions and data are
clocked in on this pin on the rising edge of JTCLK. If boundary scan is not used, JTDI should be left
unconnected or pulled high.
JTDO
O
JTAG IEEE 1149.1 Test Serial-Data Output. Test instructions and data are clocked out on this pin on
the falling edge of JTCLK.
JTRST
IPU
JTAG IEEE 1149.1 Test Reset (Internal 10k
Pullup to VDD). This pin is used to asynchronously
reset the test access port (TAP) controller. If boundary scan is not used,
JTRST can be held low or
high.
JTMS
IPU
JTAG IEEE 1149.1 Test Mode Select (Internal 10k
Pullup to VDD). This pin is sampled on the rising
edge of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If boundary
scan is not used, JTMS should be left unconnected or pulled high.
RST
IPU
Reset Input (Active Low, Open Drain, Internal 10k
Pullup to VDD). When this global asynchronous
reset is pulled low, the internal circuitry is reset and the internal registers (CPU bus mode) are forced to
their default values. The device is held in reset as long as
RST is low. RST should be held low for at
least two master clock cycles. See Section 13 for more information.
TEST
IPU
Factory Test Pin. Leave unconnected or wire high for normal operation.
VDD
P
Positive Supply. 3.3V
±5%. All VDD signals should be wired together.
VSS
P
Ground Reference. All VSS signals should be wired together.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3254N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254N# | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3254NA3 | 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube |
| DS3256 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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