參數(shù)資料
型號(hào)： DS3254DK
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 19/71頁(yè)
文件大小： 0K
描述： KIT DEMO FOR DS3254
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計(jì)資源： DS3254DK Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS3254
已供物品： 板，CD
DS3251/DS3252/DS3253/DS3254
26 of 71
In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on RDAT
causes one of the following code violations:
Hardware mode or ITU bit set to 0
–
A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V).
–
A BPV with the same polarity as the last BPV.
–
The fourth zero in an EXZ occurrence (only in hardware mode or when ITU = 0).
ITU bit set to 1
–
A BPV with the same polarity as the last BPV.
When RLCV is asserted to flag a BPV, the RDAT pin outputs a one. The state bit that tracks the polarity of the last
BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.
To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be inverted.
Normally, data is output on the RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK. To output data on
these pins on the rising edge of RCLK, pull the RCINV pin high (hardware mode) or set the RCINV configuration bit
in the RCR register (CPU bus mode).
The RCLK, RPOS/RDAT, and RNEG/RLCV pins can be tri-stated to support protection switching and redundant-
LIU applications. This tri-stating capability supports system configurations where two or more LIUs are wire-ORed
together and a system processor selects one to be active. To tri-state RCLK, RPOS/RDAT, and RNEG/RLCV,
assert the
RTS pin or the RTS configuration bit in the RCR register.
8.7 Receive Line-Code Violation Counter
The line-code violation counter is always enabled regardless of the settings of the RBIN pin or the RBIN
configuration bit. The receiver has an internal 16-bit saturating counter and a 16-bit latch, which the CPU can read
as registers RCVH and RCVL. The value of the internal counter is latched into the RCVH/RCVL register and
cleared when the receive code-violation counter update bit, RCR:RCVUD, is changed from a zero to a one. The
RCVUD bit must be cleared back to a zero before a new update can occur. If there is an LCV increment pulse and
an update pulse in the same clock period, the counter is preset to a one rather than cleared so that the LCV is not
missed. The counter is incremented when the RLCV pin flags a code violation as described in Section 8.6. The
counter saturates at 65,535 (0FFFFh) and does not roll over.
8.8 Receiver Power-Down
To minimize power consumption when the receiver is not being used, assert the RPD configuration bit in the RCR
register (CPU bus mode). When the receiver is powered down, the RCLK, RPOS/RDAT, and RNEG/RLCV pins are
tri-stated. In addition, the RXP and RXN pins become high impedance.
8.9 Receiver Jitter Tolerance
The receiver exceeds the input jitter tolerance requirements of all applicable telecommunication standards in Table
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參數(shù)描述
DS3254N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254N# 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254NA3 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube
DS3256 功能描述:網(wǎng)絡(luò)控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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