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參數(shù)資料
| 型號： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數(shù)： | 39/114頁 |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1628 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
37
4 Hardware Architecture
(continued)
The frequency of the PLL output clock, f
VCO
, is deter-
mined by the values loaded into the 3-bit N divider and
the 5-bit M divider. When the PLL is selected and
locked, the frequency of the internal processor clock is
related to the frequency of CKI by the following equa-
tions:
f
VCO
= f
CKI
* M/N
f
INTERNAL CLOCK
= f
CKO
= f
VCO
÷
2
The frequency of the VCO, f
VCO
, must fall within the
range listed in Table 63. Also note that f
VCO
must be at
least twice f
CKI
.
The coding of the Mbits and Nbits is described as fol-
lows:
Mbits = M
2
if (N = 1)
Nbits = 0x7
else
Nbits = N
2
where N ranges from 1 to 8 and M ranges from 2 to 20.
The loop filter bits LF[3:0] should be programmed ac-
cording to Table 64.
Two other bits in the
pllc
register control the PLL. Clear-
ing the PLLEN bit powers down the PLL; setting this bit
powers up the PLL. Clearing the PLLSEL bit deselects
the PLL so that the DSP is clocked by a 1X version of
the CKI input; setting the PLLSEL bit selects the PLL-
generated clock for the source of the DSP internal pro-
cessor clock. The
pllc
register is cleared on reset and
powerup. Therefore, the DSP comes out of reset with
the PLL deselected and powered down. M and N should
be changed only while the PLL is deselected. The val-
ues of M and N should not be changed when powering
down or deselecting the PLL.
As previously mentioned, the PLL also provides a user
flag, LOCK, to indicate when the loop has locked. When
this flag is not asserted, the PLL output is unstable. The
DSP should not be switched to the PLL-based clock
without first checking that the lock flag is set. The lock
flag is cleared by writing to the
pllc
register. When the
PLL is deselected, it is necessary to wait for the PLL to
relock before the DSP can be switched to the PLL-
based clock. Before the input clock is stopped, the PLL
should be powered down. Otherwise, the LOCK flag will
not be reset and there may be no way to determine if the
PLL is stable, once the input clock is applied again.
The lock-in time depends on the frequency of operation
and the values programmed for M and N (see Table 64).
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