- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377000 > DSP1628 TVS 400W 60V BIDIRECT SMA PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 41/114頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1628 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)當(dāng)前第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
39
4 Hardware Architecture
(continued)
4.14 Power Management
There are three different control mechanisms for putting
the DSP1628 into low-power modes: the
powerc
con-
trol register, the STOP pin, and the AWAIT bit in the
alf
register. The PLL can also be disabled with the PLLEN
bit of the
pllc
register for more power saving.
Powerc Control Register Bits
The
powerc
register has 10 bits that power down vari-
ous portions of the chip and select the clock source:
XTLOFF: Assertion of the XTLOFF bit powers down the
small-signal input circuit, disabling the internal proces-
sor clock. Since the small-signal input circuit takes
many cycles to stabilize, care must be taken with the
turn-on sequence, as described later.
SLOWCKI: Assertion of the SLOWCKI bit selects the
ring oscillator as the clock source for the internal pro-
cessor clock instead of CKI or the PLL. When CKI or the
PLL is selected, the ring oscillator is powered down.
Switching of the clocks is synchronized so that no par-
tial or short clock pulses occur. Two
nop
s should follow
the instruction that sets or clears SLOWCKI.
NOCK: Assertion of the NOCK bit synchronously turns
off the internal processor clock, regardless of whether
its source is provided by CKI, the PLL, or the ring oscil-
lator. The NOCK bit can be cleared by resetting the chip
with the RSTB pin, or asserting the INT0 or INT1 pins.
Two
nop
s should follow the instruction that sets NOCK.
The PLL remains running, if enabled, while NOCK is
set.
INT0EN: This bit allows the INT0 pin to asynchronously
clear the NOCK bit, thereby allowing the device to con-
tinue program execution from where it left off without
any loss of state. No chip reset is required. It is recom-
mended that, when INT0EN is to be used, the INT0
interrupt be disabled in the
inc
register so that an unin-
tended interrupt does not occur. After the program re-
sumes, the INT0 interrupt in the
ins
register should be
cleared.
INT1EN: This bit enables the INT1 pin to be used as the
NOCK clear, exactly like INT0EN previously described.
The following control bits power down the peripheral
I/O units of the DSP. These bits can be used to further
reduce the power consumption during standard sleep
mode.
SIO1DIS: This is a powerdown signal to the SIO1 I/O
unit. It disables the clock input to the unit, thus elimi-
nating any sleep power associated with the SIO1.
Since the gating of the clocks may result in incomplete
transactions, it is recommended that this option be
used in applications where the SIO1 is not used or
when reset may be used to reenable the SIO1 unit.
Otherwise, the first transaction after reenabling the unit
may be corrupted.
SIO2DIS: This bit powers down the SIO2 in the same
way SIO1DIS powers down the SIO1.
PHIFDIS: This is a powerdown signal to the parallel
host interface. It disables the clock input to the unit,
thus eliminating any sleep power associated with the
PHIF. Since the gating of the clocks may result in in-
complete transactions, it is recommended that this op-
tion be used in applications where the PHIF is not
used, or when reset may be used to reenable the
PHIF. Otherwise, the first transaction after reenabling
the unit may be corrupted.
TIMERDIS: This is a timer disable signal which dis-
ables the clock input to the timer unit. Its function is
identical to the DISABLE field of the
timerc
control
register. Writing a 0 to the TIMERDIS field will continue
the timer operation.
Figure 11 shows a functional view of the effect of the
bits of the
powerc
register on the clock circuitry. It
shows only the high-level operation of each bit. Not
shown are the bits that power down the peripheral
units.
STOP Pin
Assertion (active-low) of the STOP pin has the same
effect as setting the NOCK bit in the
powerc
register.
The internal processor clock is synchronously disabled
until the STOP pin is returned high. Once the STOP
pin is returned high, program execution will continue
from where it left off without any loss of state. No chip
reset is required. The PLL remains running, if enabled,
during STOP assertion.
The pllc Register Bits
The PLLEN bit of the
pllc
register can be used to pow-
er down the clock synthesizer circuitry. Before shutting
down the clock synthesizer circuitry, the system clock
should be switched to either CKI using the PLLSEL bit
of
pllc
, or to the ring oscillator using the SLOWCKI bit
of
powerc
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP16210 | TVS 400W 6.5V UNIDIRECT SMA |
| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
| DSP16410 | 16-bit fixed point DSP with Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP1629 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1629 Digital Signal Processor |
| DSP1629BA10K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|BGA|144PIN|PLASTIC |
| DSP1629BA10K12.5IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| DSP1629BA10K16.7IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|BGA|144PIN|PLASTIC |
| DSP1629BA10K19.2IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。