VDD should not be allowed to ri" />
參數(shù)資料
型號： DSP56852VFE
廠商： Freescale Semiconductor
文件頁數(shù)： 13/48頁
文件大?。?/td> 0K
描述： IC DSP 16BIT 120MHZ 81-MAPBGA
標準包裝： 348
系列： 568xx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 120MHz
連通性： EBI/EMI，SCI，SPI，SSI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 11
程序存儲器容量： 12KB（6K x 16）
程序存儲器類型： SRAM
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.3 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 81-LFBGA
包裝： 托盤
56852 Technical Data, Rev. 8
20
Freescale Semiconductor
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD
supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from
rising faster than VDDIO.
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches
approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
VDDIO > VDD > (VDDIO - 2.1V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.
Figure 4-3 Example Circuit to Control Supply Sequencing
4.4 AC Electrical Characteristics
Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8V and a VIH minimum of 2.0V for
all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of
VIH and VIL for an input signal are shown.
Figure 4-4 Input Signal Measurement References
3.3V
Regulator
1.8V
Regulator
Supply
VDD
VDDIO, VDDA
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low
High
90%
50%
10%
Rise Time
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