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參數(shù)資料
| 型號： | DSP56852VFE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 44/48頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 120MHZ 81-MAPBGA |
| 標(biāo)準包裝： | 348 |
| 系列： | 568xx |
| 核心處理器： | 56800E |
| 芯體尺寸： | 16-位 |
| 速度： | 120MHz |
| 連通性： | EBI/EMI，SCI，SPI，SSI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 11 |
| 程序存儲器容量： | 12KB（6K x 16） |
| 程序存儲器類型： | SRAM |
| RAM 容量： | 4K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.3 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 81-LFBGA |
| 包裝： | 托盤 |
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56852 Description
56852 Technical Data, Rev. 8
Freescale Semiconductor
5
1.1.4
Energy Information
Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
Wait and Stop modes available
1.2 56852 Description
The 56852 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56852 is well-suited for many applications. The
56852 includes many peripherals especially useful for low-end Internet appliance applications and
low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems
such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote
metering; and sonic alarms.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact DSP and
control code. The instruction set is also highly efficient for C-Compilers, enabling rapid development of
optimized control applications.
The 56852 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56852 also provides two external
dedicated interrupt lines, and up to 11 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56852 includes 6K words of Program RAM, 4K words of Data RAM and 1K of Boot RAM. It also
supports program execution from external memory.
This controller also provides a full set of standard programmable peripherals that include one improved
Synchronous Serial Interface (SSI) or one Serial Peripheral Interface (SPI), one Serial Communications
Interface (SCI), and one Quad Timer. The SSI, SPI, SCI I/O and three chip selects can be used as General
Purpose Input/Outputs when its primary function is not required. The SSI and SPI share I/O, so, at most,
one of these two peripherals can be in use at any time.
1.3 State of the Art Development Environment
Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
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