參數(shù)資料
型號(hào): DSP56F827FG80E
廠商: Freescale Semiconductor
文件頁數(shù): 10/60頁
文件大?。?/td> 0K
描述: IC HYBRID CTRLR 16BIT 128-LQFP
標(biāo)準(zhǔn)包裝: 72
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 64
程序存儲(chǔ)器容量: 136KB(68K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 5K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 2.75 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 128-LQFP
包裝: 托盤
56F827 Technical Data, Rev. 12
18
Freescale Semiconductor
PCS2
84
Input/Output
Programmable Chip Select - PCS 2-7 is asserted low for external peripheral
chip select.
PCS3
85
Input/Output
PCS4
86
Input/Output
PCS5
87
Input/Output
PCS6
88
Input/Output
PCS7
89
Input/Output
ANA0
70
Input
ANA0
9—Analog inputs to ADC
ANA1
71
Input
ANA2
72
Input
ANA3
73
Input
ANA4
74
Input
ANA5
75
Input
ANA6
76
Input
ANA7
77
Input
ANA8
78
Input
ANA9
79
Input
VREFN
66
Input
ADC Reference—This pin is connected to the negative side of the ADC input
range. This pin requires a 0.1
μF ceramic capacitor to VSSA and a start-up time
of 25ms, prior to beginning conversions.
VREFP
65
Input
ADC Reference—This pin is connected to the positive side of the ADC input
range. This pin requires a 0.1
μF ceramic capacitor to VSSA and a start-up time
of 25ms, prior to beginning conversions.
VREFMID
68
Input
ADC Reference—This pin isconnected to the center of the ADC input range.
This pin requires a 0.1
μF ceramic capacitor to VSSA and a start-up time of
25ms, prior to beginning conversions.
VREFLO
64
Input
ADC Reference—These pins are Negative Reference for ADC and are
generally connected to a VSSA.
VREFHI
67
Input
ADC Reference—These pins are Positive Reference for ADC and are
generally connected to a 3.3V Analog (VDDA_ADC) supply.
IRQA
40
Input
(Schmitt)
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor will
exit the Stop state.
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
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