tDRD 0— ns R" />
參數資料
型號: DSP56F827FG80E
廠商: Freescale Semiconductor
文件頁數: 28/60頁
文件大小: 0K
描述: IC HYBRID CTRLR 16BIT 128-LQFP
標準包裝: 72
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設備: POR,PWM,WDT
輸入/輸出數: 64
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 5K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 2.75 V
數據轉換器: A/D 10x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 128-LQFP
包裝: 托盤
56F827 Technical Data, Rev. 12
34
Freescale Semiconductor
Input Data Hold to RD Deasserted
tDRD
0—
ns
RD Assertion Width
Wait states = 0
Wait states > 0
tRD
19
(T*WS) + 19
ns
Address Valid to Output Data Valid
Wait states = 0
Wait states > 0
tAD
1
(T*WS) + 1
ns
Address Valid to RD Asserted
tARDA
-4.4
ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD
2.4
(T*WS) + 2.4
ns
WR Deasserted to RD Asserted
tWRRD
6.8
ns
RD Deasserted to RD Asserted
tRDRD
0—
ns
WR Deasserted to WR Asserted
tWRWR
14.1
ns
RD Deasserted to WR Asserted
tRDWR
12.8
ns
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 3-10 External Bus Asynchronous Timing1, 2 (Continued)
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic
Symbol
Min
Max
Unit
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