參數(shù)資料
型號: DSP56F827FG80E
廠商: Freescale Semiconductor
文件頁數(shù): 11/60頁
文件大?。?/td> 0K
描述: IC HYBRID CTRLR 16BIT 128-LQFP
標(biāo)準(zhǔn)包裝: 72
系列: 56F8xx
核心處理器: 56800
芯體尺寸: 16-位
速度: 80MHz
連通性: EBI/EMI,SCI,SPI,SSI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 64
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 5K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 2.75 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 128-LQFP
包裝: 托盤
Signals and Package Information
56F827 Technical Data, Rev. 12
Freescale Semiconductor
19
IRQB
49
Input
(Schmitt)
External Interrupt Request B—The IRQB input is an external interrupt
request that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for wired-OR
operation.
RESET
42
Input
(Schmitt)
Reset—This input is a direct hardware reset on the processor. When RESET
is asserted low, the device is initialized and placed in the Reset state. A
Schmitt trigger input is used for noise immunity. When the RESET pin is
deasserted, the initial chip operating mode is latched from the external boot
pin. The internal reset signal will be deasserted synchronous with the internal
clocks, after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be asserted
together. The only exception occurs in a debugging environment when a
hardware device reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.
EXTBOOT
39
Input
(Schmitt)
External Boot—This input is tied to VDD to force device to boot from off-chip
memory. Otherwise, it is tied to VSS.
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
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