參數(shù)資料
型號(hào)： DSP56F827FG80E
廠商： Freescale Semiconductor
文件頁數(shù)： 8/60頁
文件大?。?/td> 0K
描述： IC HYBRID CTRLR 16BIT 128-LQFP
標(biāo)準(zhǔn)包裝： 72
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 80MHz
連通性： EBI/EMI，SCI，SPI，SSI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器容量： 136KB（68K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 5K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 2.75 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 128-LQFP
包裝： 托盤
56F827 Technical Data, Rev. 12
16
Freescale Semiconductor
STD
(GPIOC3)
52
Output
Input/Output
SSI Transmit Data (STD)—This output pin transmits serial data from the SSI
Transmitter Shift Register.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
STFS
(GPIOC4)
51
Input
Input/Output
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by
the Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be
used by both the transmitter and receiver in synchronous mode. It is used to
synchronize data transfer and can be an input or output pin.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
STCK
(GPIOC5)
50
Input/ Output
Input/Output
SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial
bit rate clock for the transmit section of the SSI. The clock signal can be
continuous or gated. It can be used by both the transmitter and receiver in
synchronous mode.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SCLK
(GPIOF4)
102
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking
slaved listeners. In slave mode, this pin serves as the data clock input.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SCLK.
MOSI
(GPIOF5)
101
Input/Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data
on the MOSI line a half-cycle before the clock edge that the slave device uses
to latch the data.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
MISO
(GPIOF6)
100
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if the slave device is not selected.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is MISO.
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F827FG80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
DSP56F827FG80E 制造商:Freescale Semiconductor 功能描述:DSP LQFP128 3.6V
DSP56F827PB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F827 16-Bit Hybrid Controller Product Brief
DSP56F827PB/D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F827 16-bit Hybrid Controller
DSP56F8XXBLUM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F8xx Serial Bootloader User Manual
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