參數(shù)資料
型號(hào)： DSP56F827FG80E
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 6/60頁(yè)
文件大小： 0K
描述： IC HYBRID CTRLR 16BIT 128-LQFP
標(biāo)準(zhǔn)包裝： 72
系列： 56F8xx
核心處理器： 56800
芯體尺寸： 16-位
速度： 80MHz
連通性： EBI/EMI，SCI，SPI，SSI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器容量： 136KB（68K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 5K x 16
電壓 - 電源 (Vcc/Vdd)： 2.25 V ~ 2.75 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 128-LQFP
包裝： 托盤
56F827 Technical Data, Rev. 12
14
Freescale Semiconductor
RD
15
Output
Read Enable—RD is asserted during external memory read cycles. When RD
is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device data bus. When RD is deasserted high, the external
data is latched inside the device. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
WR
16
Output
Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the device puts data on
the bus. When WR is deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS
pins. WR can be connected directly to the WE pin of a Static RAM.
TA0
(GPIOF0)
112
Input/Output
TA0–3—Timer A Channels 0, 1, 2, and 3
Port F GPIO—These four General Purpose I/O (GPIO) pins can be
individually programmed as input or output.
After reset, the default state is Quad Timer.
TA1
(GPIOF1)
111
TA2
(GPIOF2)
110
TA3
(GPIOF3)
109
TCK
44
Input
(Schmitt)
Test Clock Input—This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
TMS
46
Input
(Schmitt)
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
TDI
48
Input
(Schmitt)
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
TDO
47
Input/Output
Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
TRST
45
Input
(Schmitt)
Test Reset—As an input, a low signal on this pin provides a reset signal to the
JTAG TAP controller. To ensure complete hardware reset, TRST should be
asserted whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware device reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET,
but do not assert TRST. TRST must always be asserted at power-up.
Note:
For normal operation, connect TRST directly to VSS. If the design is to be
used in a debugging environment, TRST may be tied to VSS through a 1K resistor.
DE
41
Output
Debug Event—DE provides a low pulse on recognized debug events.
Table 2-2 56F827 Signal and Package Information for the 128 Pin LQFP (Continued)
Signal Name
Pin No.
Type
Description
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