107
SAM4CP [DATASHEET]
43051E–ATPL–08/14
Condition Flags
If
S
is specified, these instructions:
Update the N and Z flags according to the result.
Can update the C flag during the calculation of
Operand2
, see
“Flexible Second Operand”
.
Do not affect the V flag.
Examples
AND
ORREQ
ANDS
EORS
BIC
ORN
ORNS
R9, R2, #0xFF00
R2, R0, R5
R9, R8, #0x19
R7, R11, #0x18181818
R0, R1, #0xab
R7, R11, R14, ROR #4
R7, R11, R14, ASR #32
12.6.5.3 ASR, LSL, LSR, ROR, and RRX
Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
Syntax
op
{S}{
cond
}
Rd
,
Rm
,
Rs
op
{S}{
cond
}
Rd
,
Rm
, #
n
RRX{S}{
cond
}
Rd
,
Rm
where:
op
is one of:
ASR Arithmetic Shift Right.
LSL Logical Shift Left.
LSR Logical Shift Right.
ROR Rotate Right.
S
is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation,
see
“Conditional Execution”
.
Rd
is the destination register.
Rm
is the register holding the value to be shifted.
Rs
is the register holding the shift length to apply to the value in
Rm
. Only the least significant byte is used
and can be in the range 0 to 255.
n
is the shift length. The range of shift length depends on the instruction:
ASR shift length from 1 to 32
LSL shift length from 0 to 31
LSR shift length from 1 to 32
ROR shift length from 0 to 31
MOVS Rd, Rm is the preferred syntax for LSLS Rd, Rm, #0.
Operation
ASR, LSL, LSR, and ROR move the bits in the register
Rm
to the left or right by the number of places specified by
constant
n
or register
Rs
.
RRX moves the bits in register
Rm
to the right by 1.
In all these instructions, the result is written to
Rd
, but the value in register
Rm
remains unchanged. For details on what
result is generated by the different instructions, see
“Shift Operations”
.