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型號(hào)：	EF4442CMG/B(Z63)
廠商：	ATMEL CORP
元件分類：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, CDIP28
封裝：	SIDE BRAZED, CERAMIC, DIP-28
文件頁(yè)數(shù)：	534/1069頁(yè)
文件大?。?/td>	14303K
代理商：	EF4442CMG/B(Z63)

SAM4CP [DATASHEET]

43051E–ATPL–08/14

29.6.1 Divider and Phase Lock Loop Programming

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the

corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the

corresponding PLL input clock is set to 0.

The PLLs (PLLA, PLLB) allow multiplication of the SLCK clock source for PLLA or PLLA output clock or MAINCK divided

output for PLLB. The PLL clock signal has a frequency that depends on the respective source signal frequency and on

the parameters DIV (DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is (MUL + 1)/DIV.

When MUL is written to 0 or PLLAEN=0, the PLL is disabled and its power consumption is saved. Re-enabling the PLL

can be performed by writing a value higher than 0 in the MUL field and PLLAEN higher than 0.

To change the frequency of the PLLA, the PLLA must be first disabled by writing 0 in MULA field and 0 in PLLACOUNT

field. Then, the PLLA can be configured to generate the new frequency by programming a new multiplier in MULA and

the PLLACOUNT field in the same register access. See electrical characteristics to get the PLLACOUNT values covering

the PLL transient time.

Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA, LOCKB) bit in PMC_SR is

automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT, PLLBCOUNT) in CKGR_PLLR

(CKGR_PLLAR, CKGR_PLLBR) are loaded in the PLL counter. The PLL counter then decrements at the speed of the

Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor.

The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field.

The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC Master Clock Register

The PLLADIV2 has no effect on PLLB clock input because the output of the PLLA is directly routed to PLLB input

It is prohibited to change the 4/8/12 MHz Fast RC Oscillator, or the main oscillator selection in CKGR_MOR while the

Master Clock source is the PLL and the PLL reference clock is the Fast RC Oscillator.

The user must:

Switch on the Main RC oscillator by writing a 1 to the CSS field of PMC_MCKR.

Change the frequency (MOSCRCF) or oscillator selection (MOSCSEL) in CKGR_MOR.

Wait for MOSCRCS (if frequency changes) or MOSCSELS (if oscillator selection changes) in PMC_SR.

Disable and then enable the PLL (LOCKx in PMC_IDR and PMC_IER).

Wait for the LOCK flag in PMC_SR.

Switch back to the PLL by writing the appropriate value to the CSS field of PMC_MCKR.

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