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型號(hào)：	EF4442CMG/B(Z63)
廠商：	ATMEL CORP
元件分類(lèi)：	通信及網(wǎng)絡(luò)
英文描述：	SPECIALTY TELECOM CIRCUIT, CDIP28
封裝：	SIDE BRAZED, CERAMIC, DIP-28
文件頁(yè)數(shù)：	743/1069頁(yè)
文件大?。?/td>	14303K
代理商：	EF4442CMG/B(Z63)

SAM4CP [DATASHEET]

43051E–ATPL–08/14

36.6.1.2 Fractional Baud Rate in Asynchronous Mode

The Baud Rate generator is subject to the following limitation: the output frequency changes only by integer multiples of

the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high

resolution. The generator architecture is modified to obtain baud rate changes by a fraction of the reference source clock.

This fractional part is programmed with the FP field in the US_BRGR. If FP is not 0, the fractional part is activated. The

resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The

fractional baud rate is calculated using the following formula:

The modified architecture is presented in the following figure:

Figure 36-3.

Fractional Baud Rate Generator

36.6.1.3 Baud Rate in Synchronous Mode or SPI Mode

If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in the

In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the

USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must

be at least 3 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLKO set to 1), the

receive part limits the SCK maximum frequency to f

peripheral clock

/3 in USART mode, or f

peripheral clock

/6 in SPI mode.

When either the external clock SCK or the internal clock divided (peripheral clock/DIV) is selected, the value

programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. When the Peripheral

Clock is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in

36.6.1.4 Baud Rate in ISO 7816 Mode

The ISO7816 specification defines the bit rate with the following formula:

-----------SelectedClock

Peripheral clock/DIV

16-bit Counter

Peripheral clock

SelectedClock

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