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參數(shù)資料
| 型號： | EP4CGX110DF31I7N |
| 廠商： | Altera |
| 文件頁數(shù)： | 16/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CYCLONE IV FPGA 110K 896FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 特色產(chǎn)品： | Cyclone? IV FPGAs |
| 標準包裝： | 27 |
| 系列： | CYCLONE® IV GX |
| LAB/CLB數(shù)： | 6839 |
| 邏輯元件/單元數(shù)： | 109424 |
| RAM 位總計： | 5621760 |
| 輸入/輸出數(shù)： | 475 |
| 電源電壓： | 1.16 V ~ 1.24 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 896-BBGA |
| 供應商設備封裝： | 896-FBGA（31x31） |
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Chapter 1: Cyclone IV Device Datasheet
1–23
Switching Characteristics
December 2013
Altera Corporation
Table 1–23 lists the Cyclone IV GX transceiver block AC specifications.
Core Performance Specifications
The following sections describe the clock tree specifications, PLLs, embedded
multiplier, memory block, and configuration specifications for Cyclone IV Devices.
Clock Tree Specifications
Table 1–24 lists the clock tree specifications for Cyclone IV devices.
Table 1–23. Transceiver Block AC Specification for Cyclone IV GX Devices (1), (2)
Symbol/
Description
Conditions
C6
C7, I7
C8
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
PCIe Transmit Jitter Generation (3)
Total jitter at 2.5 Gbps
(Gen1)
Compliance pattern
—
0.25
—
0.25
—
0.25
UI
PCIe Receiver Jitter Tolerance (3)
Total jitter at 2.5 Gbps
(Gen1)
Compliance pattern
> 0.6
UI
GIGE Transmit Jitter Generation (4)
Deterministic jitter
(peak-to-peak)
Pattern = CRPAT
—
0.14—
—0.14
—
0.14
UI
Total jitter (peak-to-peak)
Pattern = CRPAT
—
0.279
—
0.279
—
0.279
UI
GIGE Receiver Jitter Tolerance (4)
Deterministic jitter
tolerance (peak-to-peak)
Pattern = CJPAT
> 0.4
UI
Combined deterministic
and random jitter
tolerance (peak-to-peak)
Pattern = CJPAT
> 0.66
UI
Notes to Table 1–23:
(1) Dedicated refclk pins were used to drive the input reference clocks.
(2) The jitter numbers specified are valid for the stated conditions only.
(3) The jitter numbers for PIPE are compliant to the PCIe Base Specification 2.0.
(4) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
Table 1–24. Clock Tree Performance for Cyclone IV Devices (Part 1 of 2)
Device
Performance
Unit
C6
C7
C8
C8L (1)
C9L (1)
I7
I8L (1)
A7
EP4CE6
500
437.5
402
362
265
437.5
362
402
MHz
EP4CE10
500
437.5
402
362
265
437.5
362
402
MHz
EP4CE15
500
437.5
402
362
265
437.5
362
402
MHz
EP4CE22
500
437.5
402
362
265
437.5
362
402
MHz
EP4CE30
500
437.5
402
362
265
437.5
362
402
MHz
EP4CE40
500
437.5
402
362
265
437.5
362
402
MHz
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| EP4CGX110F17C8 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX110F23C8N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Faily Overview |
| EP4CGX110F23I7N | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet |
| EP4CGX15 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview |
| EP4CGX150 | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV FPGA Device Family Overview |
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