參數(shù)資料
型號(hào)： EP4CGX110DF31I7N
廠商： Altera
文件頁數(shù)： 31/42頁
文件大?。?/td> 0K
描述： IC CYCLONE IV FPGA 110K 896FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品： Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝： 27
系列： CYCLONE® IV GX
LAB/CLB數(shù)： 6839
邏輯元件/單元數(shù)： 109424
RAM 位總計(jì)： 5621760
輸入/輸出數(shù)： 475
電源電壓： 1.16 V ~ 1.24 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 896-BBGA
供應(yīng)商設(shè)備封裝： 896-FBGA（31x31）
Chapter 1: Cyclone IV Device Datasheet
1–37
I/O Timing
December 2013
Altera Corporation
I/O Timing
Use the following methods to determine I/O timing:
■
the Excel-based I/O Timing
■
the Quartus II timing analyzer
The Excel-based I/O timing provides pin timing performance for each device density
and speed grade. The data is typically used prior to designing the FPGA to get a
timing budget estimation as part of the link timing analysis. The Quartus II timing
analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after place-and-route is complete.
f The Excel-based I/O Timing spreadsheet is downloadable from Cyclone IV Devices
Literature website.
Glossary
Table 1–46 lists the glossary for this chapter.
Table 1–46. Glossary (Part 1 of 5)
Letter
Term
Definitions
A
——
B
——
C
——
D
——
E
——
F
fHSCLK
High-speed I/O block: High-speed receiver/transmitter input and output clock frequency.
G
GCLK
Input pin directly to Global Clock network.
GCLK PLL
Input pin to Global Clock network through the PLL.
H
HSIODR
High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI).
I
Input Waveforms
for the SSTL
Differential I/O
Standard
V
IL
V
REF
V
IH
VSWING
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參數(shù)描述
EP4CGX110F17C8 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Cyclone IV Device Datasheet
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