參數(shù)資料
型號: EP4CGX110DF31I7N
廠商: Altera
文件頁數(shù): 21/42頁
文件大?。?/td> 0K
描述: IC CYCLONE IV FPGA 110K 896FBGA
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
特色產(chǎn)品: Cyclone? IV FPGAs
標(biāo)準(zhǔn)包裝: 27
系列: CYCLONE® IV GX
LAB/CLB數(shù): 6839
邏輯元件/單元數(shù): 109424
RAM 位總計(jì): 5621760
輸入/輸出數(shù): 475
電源電壓: 1.16 V ~ 1.24 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 896-BBGA
供應(yīng)商設(shè)備封裝: 896-FBGA(31x31)
1–28
Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
December 2013
Altera Corporation
f For more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to Section III: System
Performance Specifications of the External Memory Interfaces Handbook.
1 Actual achievable frequency depends on design- and system-specific factors. Perform
HSPICE/IBIS simulations based on your specific design and system setup to
determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Table 1–31 through Table 1–36 list the high-speed I/O timing for Cyclone IV devices.
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–37.
Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4) (Part 1 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
C8L, I8L
C9L
Unit
Min
Typ
Max Min
Typ
Max
Min
Typ
Min
Typ
Max
Min
Typ
Max
fHSCLK
(input clock
frequency)
×10
5
180
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×8
5
180
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×7
5
180
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×4
5
180
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×2
5
180
5
155.5
5
155.5
5
155.5
5
132.5
MHz
×1
5
360
5
311
5
311
5
311
5
265
MHz
Device
operation in
Mbps
×10
100
360
100
311
100
311
100
311
100
265
Mbps
×8
80
360
80
311
80
311
80
311
80
265
Mbps
×7
70
360
70
311
70
311
70
311
70
265
Mbps
×4
40
360
40
311
40
311
40
311
40
265
Mbps
×2
20
360
20
311
20
311
20
311
20
265
Mbps
×1
10
360
10
311
10
311
10
311
10
265
Mbps
tDUTY
45
55
45
55
45
55
45
55
45
55
%
Transmitter
channel-to-
channel skew
(TCCS)
200
200
200
200
200
ps
Output jitter
(peak to peak)
500
500
550
600
700
ps
tRISE
20 – 80%,
CLOAD =
5pF
500
500
500
500
500
ps
tFALL
20 – 80%,
CLOAD =
5pF
500
500
500
500
500
ps
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