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參數(shù)資料
| 型號： | EVAL-AD7923CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7923 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ 2.5 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 7.5mW @ 200kSPS，5 V |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7923 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | AD7923BRUZ-REEL7TR-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP AD7923BRUZ-REEL-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP AD7923BRUZ-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP |
AD7923
Data Sheet
Rev. D | Page 10 of 24
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 ... 000) to
(00 ... 001) from the ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 ... 110) to
(111 ... 111) from the ideal (that is, REFIN – 1 LSB) after the
offset error has been adjusted.
Gain Error Match
This is the difference in gain error between any two channels.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
REFIN to +REFIN is biased around the REFIN point. It defined
as the deviation of the midscale transition (all 0s to all 1s) from
the ideal VIN voltage, that is, REFIN – 1 LSB.
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
REFIN to +REFIN is biased around the REFIN point. It is the
deviation of the last code transition (011 ... 110) to (011 ... 111)
from the ideal (that is, +REFIN – 1 LSB) after the zero-code
error has been adjusted.
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular, with the 2 × REFIN input range when
REFIN to +REFIN is biased around the REFIN point. It is the
deviation of the first code transition (100 ... 000) to (100 ... 001)
from the ideal (that is, REFIN + 1 LSB) after the zero-code
error has been adjusted.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of cross-
talk between channels. It is measured by applying a full-scale
400 kHz sine wave signal to all three nonselected input channels
and determining how much that signal is attenuated in the
selected channel with a 50 kHz signal. The figure is given in the
worst-case across all four channels for the AD7923.
Power Supply Rejection (PSR)
Variations in power supply affect the full-scale transition, but
not the converter’s linearity. Power supply rejection is the maxi-
mum change in the full-scale transition point from a change in
power supply voltage from the nominal value.
Figure 6 shows the power supply rejection ratio vs. supply ripple
frequency for the AD7923 with no decoupling. The power sup-
ply rejection ratio is defined as the ratio of the power in the
ADC output at full-scale frequency, f, to the power of a 200 mV
p-p sine wave applied to the ADC AVDD supply of frequency fS:
PSSR (dB) = 10log(Pf/PfS)
Pf is equal to the power at frequency f in the ADC output; PfS is
equal to the power at frequency fS coupled onto the ADC AVDD
supply.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode at the
end of conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±1 LSB, after the end of conversion.
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