AVDD = 2.7 V to 5.25 V, " />
參數(shù)資料
型號(hào)： EVAL-AD7923CBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD7923
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 12
采樣率（每秒）： 200k
數(shù)據(jù)接口： 串行
輸入范圍： 0 ~ 2.5 V
在以下條件下的電源（標(biāo)準(zhǔn)）： 7.5mW @ 200kSPS，5 V
工作溫度： -40°C ~ 125°C
已用 IC / 零件： AD7923
已供物品： 板，CD
相關(guān)產(chǎn)品： AD7923BRUZ-REEL7TR-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP
AD7923BRUZ-REEL-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP
AD7923BRUZ-ND - IC ADC 12BIT 4CH W/SEQ 16TSSOP
Data Sheet
AD7923
Rev. D | Page 5 of 24
TIMING SPECIFICATIONS
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 2.
Limit at TMIN, TMAX
Parameter
AVDD = 3 V
AVDD = 5 V
Unit
Description
10
kHz min
20
MHz max
tCONVERT
16 × tSCLK
tQUIET
50
ns min
Minimum quiet time required between CS rising edge and start of next
conversion
t2
10
ns min
CS to SCLK set-up time
35
30
ns max
Delay from CS until DOUT three-state disabled
40
ns max
Data access time after SCLK falling edge
t5
0.4 × tSCLK
ns min
SCLK low pulse width
t6
0.4 × tSCLK
ns min
SCLK high pulse width
t7
10
ns min
SCLK to DOUT valid hold time
15/45
15/35
ns min/max
SCLK falling edge to DOUT high impedance
t9
10
ns min
DIN set-up time prior to SCLK falling edge
t10
5
ns min
DIN hold time after SCLK falling edge
t11
20
ns min
Sixteenth SCLK falling edge to CS high
t12
1
s max
Power-Up time from full power-down/auto shutdown mode
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V. See Figure 2.
The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
2
The mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, quoted in the timing characteristics t8, is the true bus relinquish
time of the part and is independent of the bus loading.
200
A
IOL
200
A
IOH
1.6V
TO OUTPUT
PIN
CL
50pF
03086-002
Figure 2. Load Circuit for Digital Output Timing Specification
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