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| 型號(hào)： | EVAL-ADUC841QSPZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV QUICK START ADUC841 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC841 |
| 所含物品： | 評(píng)估板、電源、纜線(xiàn)、軟件、仿真器和說(shuō)明文檔 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 10 of 88
Mnemonic
Type
Function
P3.0–P3.7
I/O
Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high
by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled
externally low source current because of the internal pull-up resistors. Port 3 pins also contain various secondary
functions, which are described below.
PWMC
I
PWM Clock Input.
PWM0
O
PWM0 Voltage Output. PWM outputs can be configured to use Ports 2.6 and 2.7 or Ports 3.4 and 3.3.
PWM1
O
PWM1 Voltage Output. See the CFG841/CFG842 register for further information.
RxD
I/O
Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of the Serial (UART) Port.
TxD
O
Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of the Serial (UART) Port.
INT0
I
Interrupt 0. Programmable edge or level triggered interrupt input; can be programmed to one of two priority
levels. This pin can also be used as a gate control input to Timer 0.
INT1
I
Interrupt 1. Programmable edge or level triggered interrupt input; can be programmed to one of two priority
levels. This pin can also be used as a gate control input to Timer 1.
T0
I
Timer/Counter 0 Input.
T1
I
Timer/Counter 1 Input.
CONVST
I
Active Low Convert Start Logic Input for the ADC Block when the External Convert Start Function is Enabled. A
low-to-high transition on this input puts the track-and-hold into hold mode and starts the conversion.
EXTCLK
I
Input for External Clock Signal. Has to be enabled via the CFG842 register.
WR
O
Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
RD
O
Read Control Signal, Logic Output. Enables the external data memory to Port 0.
XTAL2
O
Output of the Inverting Oscillator Amplifier.
XTAL1
I
Input to the Inverting Oscillator Amplifier.
DGND
G
Digital Ground. Ground reference point for the digital circuitry.
P2.0–P2.7
(A8–A15)
(A16–A23)
I/O
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high
by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled
externally low source current because of the internal pull-up resistors. Port 2 emits the middle and high-order
address bytes during accesses to the external 24-bit external data memory space.
PSEN
O
Program Store Enable, Logic Output. This pin remains low during internal program execution. PSEN is used to
enable serial download mode when pulled low through a resistor on power-up or reset. On reset this pin will
momentarily become an input and the status of the pin is sampled. If there is no pulldown resistor in place the pin
will go momentarilly high and then user code will execute. If a pull-down resistor is in place, the embedded serial
download/debug kernel will execute.
ALE
O
Address Latch Enable, Logic Output. This output is used to latch the low byte and page byte for 24-bit address
space accesses of the address into external data memory.
EA
I
External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal
program memory locations. The parts do not support external code memory. This pin should not be left floating.
P0.7–P0.0
(A0-A7)
I/O
Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state
can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during
accesses to external data memory. In this application, it uses strong internal pull-ups when emitting 1s.
Types: P = Power, G = Ground, I= Input, O = Output., NC = No Connect
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| EVAL-ADUC841QSPZ | 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C |
| EVAL-ADUC841QSZ | 功能描述:KIT DEV FOR ADUC841 QUICK START RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 通用嵌入式開(kāi)發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類(lèi)型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線(xiàn)纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁(yè)面:659 (CN2011-ZH PDF) |
| EVAL-ADUC842QS | 功能描述:KIT DEV FOR ADUC842 QUICK START RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 通用嵌入式開(kāi)發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類(lèi)型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤(pán)，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤(pán) 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| EVAL-ADUC842QS1 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| EVAL-ADUC842QSP1 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
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