TIMING SPECIFICATIONS1, 2, 3 Table 41. " />
參數(shù)資料
型號(hào)： EVAL-ADUC841QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 76/88頁(yè)
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC841
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC841
所含物品： 評(píng)估板、電源、纜線、軟件、仿真器和說(shuō)明文檔
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 78 of 88
TIMING SPECIFICATIONS1, 2, 3
Table 41. AVDD =2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX,
unless otherwise noted
Parameter
32.768 kHz External Crystal
ADuC842/ADuC843 CLOCK INPUT (External Clock Driven XTAL1)
Min
Typ
Max
Unit
tCK
XTAL1 Period
30.52
s
tCKL
XTAL1 Width Low
6.26
s
tCKH
XTAL1 Width High
6.26
s
tCKR
XTAL1 Rise Time
9
ns
tCKF
XTAL1 Fall Time
9
ns
1/tCORE
ADuC842/ADuC843 Core Clock Frequency4
0.131
16.78
MHz
tCORE
ADuC842/ADuC843 Core Clock Period5
0.476
s
tCYC
ADuC842/ADuC843 Machine Cycle Time6
0.059
0.476
7.63
s
1 AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1 and 0.45 V for Logic 0. Timing measurements are made at VIH min for Logic 1 and VIL max for Logic 0, as
shown in Figure 87.
2 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded VOH/VOL level occurs, as shown in Figure 87.
3 CLOAD for all outputs = 80 pF, unless otherwise noted.
4 ADuC842/ADuC843 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 16.78 MHz internal clock for the
system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR.
5 This number is measured at the default Core_Clk operating frequency of 2.09 MHz.
6 ADuC842/ADuC843 machine cycle time is nominally defined as 1/Core_CLK.
Parameter
Variable External Crystal
ADuC841 CLOCK INPUT (External Clock Driven XTAL1)
Min
Typ
Max
Unit
tCK
XTAL1 Period
62.5
1000
ns
tCKL
XTAL1 Width Low
20
ns
tCKH
XTAL1 Width High
20
ns
tCKR
XTAL1 Rise Time
20
ns
tCKF
XTAL1 Fall Time
20
ns
1/tCORE
ADuC841 Core Clock Frequency
0.131
20
MHz
tCORE
ADuC841 Core Clock Period
0.476
s
tCYC
ADuC841 Machine Cycle Time
0.05
0.476
7.63
s
t
CKH
t
CKL
t
CK
t
CKF
t
CKR
03260-0-085
Figure 86. XTAL1 Input
DVDD – 0.5V
0.45V
0.2DVDD + 0.9V
TEST POINTS
0.2DVDD – 0.1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
VLOAD – 0.1V
VLOAD
VLOAD – 0.1V
03260-0-086
Figure 87. Timing Waveform Characteristics
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參數(shù)描述
EVAL-ADUC841QSPZ 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C
EVAL-ADUC841QSZ 功能描述:KIT DEV FOR ADUC841 QUICK START RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁(yè)面:659 (CN2011-ZH PDF)
EVAL-ADUC842QS 功能描述:KIT DEV FOR ADUC842 QUICK START RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
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EVAL-ADUC842QSP1 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU
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