參數(shù)資料
型號(hào)： EVAL-ADUC841QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 37/88頁(yè)
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC841
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： ADuC841
所含物品： 評(píng)估板、電源、纜線(xiàn)、軟件、仿真器和說(shuō)明文檔
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 42 of 88
PULSE-WIDTH MODULATOR (PWM)
The PWM on the ADuC841/ADuC842/ADuC843 is a highly
flexible PWM offering programmable resolution and an input
clock, and can be configured for any one of six different modes
of operation. Two of these modes allow the PWM to be config-
ured as a ∑- DAC with up to 16 bits of resolution. A block
diagram of the PWM is shown in Figure 47. Note the PWM
clock’s sources are different for the ADuC841, and are given in
Table 17.
CLOCK
SELECT
PROGRAMMABLE
DIVIDER
COMPARE
MODE
PWM0H/L
PWM1H/L
f
VCO
TO/EXTERNAL PWM CLOCK
fXTAL/15
fXTAL
P2.6
P2.7
16-BIT PWM COUNTER
03260-0-046
Figure 47. PWM Block Diagram
The PWM uses five SFRs: the control SFR (PWMCON) and
four data SFRs (PWM0H, PWM0L, PWM1H, and PWM1L).
PWMCON, as described in the following sections, controls the
different modes of operation of the PWM as well as the PWM
clock frequency.
PWM0H/L and PWM1H/L are the data registers that deter-
mine the duty cycles of the PWM outputs. The output pins that
the PWM uses are determined by the CFG841/CFG842 register,
and can be either P2.6 and P2.7 or P3.4 and P3.3. In this section
of the data sheet, it is assumed that P2.6 and P2.7 are selected as
the PWM outputs.
To use the PWM user software, first write to PWMCON to
select the PWM mode of operation and the PWM input clock.
Writing to PWMCON also resets the PWM counter. In any of
the 16-bit modes of operation (Modes 1, 3, 4, 6), user software
should write to the PWM0L or PWM1L SFRs first. This value is
written to a hidden SFR. Writing to the PWM0H or PWM1H
SFRs updates both the PWMxH and the PWMxL SFRs but does
not change the outputs until the end of the PWM cycle in
progress. The values written to these 16-bit registers are then
used in the next PWM cycle.
PWMCON PWM
Control SFR
SFR Address
AEH
Power-On Default
00H
Bit Addressable
No
Table 17. PWMCON SFR Bit Designations
Bit No.
Name
Description
7
SNGL
Turns off PMW output at P2.6 or P3.4, leaving the port pin free for digital I/O.
6
MD2
PWM Mode Bits.
5
MD1
The MD2/1/0 bits choose the PWM mode as follows:
MD2
MD1
MD0
Mode
0
Mode 0: PWM Disabled
0
1
Mode 1: Single variable resolution PWM on P2.7 or P3.3
0
1
0
Mode 2: Twin 8-bit PWM
0
1
Mode 3: Twin 16-bit PWM
1
0
Mode 4: Dual NRZ 16-bit ∑- DAC
1
0
1
Mode 5: Dual 8-bit PWM
1
0
Mode 6: Dual RZ 16-bit ∑- DAC
4
MD0
1
Reserved
3
CDIV1
PWM Clock Divider.
Scale the clock source for the PWM counter as follows:
CDIV1
CDIV0
Description
0
PWM Counter = Selected Clock/1
0
1
PWM Counter = Selected Clock/4
1
0
PWM Counter = Selected Clock/16
2
CDIV0
1
PWM Counter = Selected Clock/64
1
CSEL1
PWM Clock Divider.
Select the clock source for the PWM as follows:
CSEL1
CSEL0
Description
0
PWM Clock = fXTAL/15, ADuC841 = fOCS/DIVIDE FACTOR /15 (see the CFG841 register)
0
1
PWM Clock = fXTAL, ADuC841 = fOCS/DIVIDE FACTOR (see the CFG841 register)
1
0
PWM Clock = External input at P3.4/T0
0
CSEL0
1
PWM Clock = fVCO = 16.777216 MHz, ADuC841 = fOSC
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