參數(shù)資料
型號(hào)： EVAL-ADUC841QSPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 69/88頁(yè)
文件大小： 0K
描述： KIT DEV QUICK START ADUC841
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC841
所含物品： 評(píng)估板、電源、纜線、軟件、仿真器和說明文檔
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 71 of 88
IEIP2
Secondary Interrupt Enable Register
SFR Address
A9H
Power-On Default
A0H
Bit Addressable
No
Table 37. IEIP2 SFR Bit Designations
Bit No.
Name
Description
7
----
Reserved.
6
PTI
Priority for time interval interrupt.
5
PPSM
Priority for power supply monitor interrupt.
4
PSI
Priority for SPI/I2C interrupt.
3
----
This bit must contain zero.
2
ETI
Set by the user to enable, or cleared to disable time interval counter interrupts.
1
EPSMI
Set by the user to enable, or cleared to disable power supply monitor interrupts.
0
ESI
Set by the user to enable, or cleared to disable SPI or I2C serial port interrupts.
Interrupt Priority
The interrupt enable registers are written by the user to enable
individual interrupt sources, while the interrupt priority regis-
ters allow the user to select one of two priority levels for each
interrupt. An interrupt of a high priority may interrupt the
service routine of a low priority interrupt, and if two interrupts
of different priority occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, a polling sequence
is observed as shown in Table 38.
Table 38. Priority within an Interrupt Level
Source
Priority
Description
PSMI
1 (Highest)
Power Supply Monitor Interrupt.
WDS
2
Watchdog Timer Interrupt.
IE0
2
External Interrupt 0.
ADCI
3
ADC Interrupt.
TF0
4
Timer/Counter 0 Interrupt.
IE1
5
External Interrupt 1.
TF1
6
Timer/Counter 1 Interrupt.
ISPI/I2CI
7
SPI Interrupt/I2C Interrupt.
RI + TI
8
Serial Interrupt.
TF2 + EXF2
9
Timer/Counter 2 Interrupt.
TII
11(Lowest)
Time Interval Counter Interrupt.
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 39.
Table 39. Interrupt Vector Addresses
Source
Vector Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI + TI
0023H
TF2 + EXF2
002BH
ADCI
0033H
ISPI/I2CI
003BH
PSMI
0043H
TII
0053H
WDS
005BH
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