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| 型號： | EVAL-ADUC841QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV QUICK START ADUC841 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC841 |
| 所含物品： | 評估板、電源、纜線、軟件、仿真器和說明文檔 |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 36 of 88
ADuC842/ADuC843 Configuration SFR (CFG842)
The CFG842 SFR contains the necessary bits to configure the
internal XRAM, external clock select, PWM output selection,
DAC buffer, and the extended SP for both the ADuC842 and the
ADuC843. By default, it configures the user into 8051 mode, i.e.,
extended SP is disabled and internal XRAM is disabled. On the
ADuC841, this register is the CFG841 register and is described
on the next page.
CFG842
ADuC842/ADuC843 Config SFR
SFR Address
AFH
Power-On Default
00H
Bit Addressable
No
Table 13. CFG842 SFR Bit Designations
Bit No.
Name
Description
7
EXSP
Extended SP Enable.
When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to 0100H.
When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H.
6
PWPO
PWM Pin Out Selection.
Set to 1 by the user to select P3.4 and P3.3 as the PWM output pins.
Set to 0 by the user to select P2.6 and P2.7 as the PWM output pins.
5
DBUF
DAC Output Buffer.
Set to 1 by the user to bypass the DAC output buffer.
Set to 0 by the user to enable the DAC output buffer.
4
EXTCLK
Set by the user to 1 to select an external clock input on P3.4.
Set by the user to 0 to use the internal PLL clock.
3
RSVD
Reserved. This bit should always contain 0.
2
RSVD
Reserved. This bit should always contain 0.
1
MSPI
Set to 1 by the user to move the SPI functionality of MISO, MOSI, and SCLOCK to P3.3, P3.4, and P3.5,
respectively.
Set to 0 by the user to leave the SPI functionality as usual on MISO, MOSI, and SCLOCK pins.
0
XRAMEN
XRAM Enable Bit.
When set to 1 by the user, the internal XRAM is mapped into the lower 2 kBytes of the external address
space.
When set to 0 by the user, the internal XRAM is not accessible, and the external data memory is
mapped into the lower 2 kBytes of external data memory.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC841QSPZ | 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C |
| EVAL-ADUC841QSZ | 功能描述:KIT DEV FOR ADUC841 QUICK START RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| EVAL-ADUC842QS | 功能描述:KIT DEV FOR ADUC842 QUICK START RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ 套件 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| EVAL-ADUC842QS1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| EVAL-ADUC842QSP1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
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