- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375916 > FS7VS-5 (Mitsubishi Electric Corporation) HIGH-SPEED SWITCHING USE PDF資料下載
參數(shù)資料
| 型號： | FS7VS-5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | HIGH-SPEED SWITCHING USE |
| 中文描述： | 高速開關(guān)使用 |
| 文件頁數(shù)： | 21/91頁 |
| 文件大小： | 488K |
| 代理商： | FS7VS-5 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁
PSD9XX Family
PSD935G2
20
The
PSD935G2
Functional
Blocks
(cont.)
9.1.1.6.5 Data Polling Flag DQ7
When Erasing or Programming the Flash memory bit DQ7 outputs the complement of the
bit being entered for Programming/Writing on DQ7. Once the Program instruction or the
Write operation is completed, the true logic value is read on DQ7 (in a Read operation).
Flash memory specific features:
J
Data Polling is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase). It must be performed at the address being programmed
or at an address within the Flash sector being erased.
J
During an Erase instruction, DQ7 outputs a
‘
0
’
. After completion of the instruction,
DQ7 will output the last bit programmed (it is a
‘
1
’
after erasing).
J
If the location to be programmed is in a protected Flash sector, the instruction is
ignored.
J
If all the Flash sectors to be erased are protected, DQ7 will be set to
‘
0
’
for
about 100 μs, and then return to the previous addressed location. No erasure will be
performed.
9.1.1.6.6 Toggle Flag DQ6
The PSD935G2 offers another way for determining when the Flash memory Program
instruction is completed. During the internal Write operation and when either the FSi or
CSBOOTi is true, the DQ6 will toggle from
‘
0
’
to
‘
1
’
and
‘
1
’
to
‘
0
’
on subsequent attempts to
read any byte of the memory.
When the internal cycle is complete, the toggling will stop and the data read on the
Data Bus D0-7 is the addressed memory location. The device is now accessible for a new
Read or Write operation. The operation is finished when two successive reads yield the
same output data. Flash memory specific features:
J
The Toggle bit is effective after the fourth Write pulse (for programming) or after the
sixth Write pulse (for Erase).
J
If the location to be programmed belongs to a protected Flash sector, the instruction
is ignored.
J
If all the Flash sectors selected for erasure are protected, DQ6 will toggle to
‘
0
’
for
about 100 μs and then return to the previous addressed location.
9.1.1.6.7 Error Flag DQ5
During a correct Program or Erase, the Error bit will set to
‘
0
’
. This bit is set to
‘
1
’
when
there is a failure during Flash programming, Sector erase, or Bulk Erase.
In the case of Flash programming, the Error Bit indicates the attempt to program a Flash
bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation.
The Error bit may also indicate a timeout condition while attempting to program a byte.
In case of an error in Flash sector erase or byte program, the Flash sector in which the
error occurred or to which the programmed location belongs must no longer be used.
Other Flash sectors may still be used. The Error bit resets after the Reset instruction.
9.1.1.6.8 Erase Time-out Flag DQ3
The Erase Timer bit reflects the time-out period allowed between two consecutive Sector
Erase instructions. The Erase timer bit is set to
‘
0
’
after a Sector Erase instruction for a
time period of 100 μs + 20% unless an additional Sector Erase instruction is decoded.
After this time period or when the additional Sector Erase instruction is decoded, DQ3 is
set to
‘
1
’
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD935F3V-15B81 | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935F3V-15B81I | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 30000uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-0.1pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate |
| PSD935F3V-15J | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935F3V-15JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935F3V-15M | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS-8000 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:MULTI-USER KVM SWITCH |
| FS-80-0-300V | 制造商:Fuji Electric 功能描述: |
| FS800R06KE3_H7E | 制造商:Infineon Technologies AG 功能描述: |
| FS800R07A2E3 | 功能描述:IGBT 模塊 IGBT Module 650V 700A RoHS:否 制造商:Infineon Technologies 產(chǎn)品:IGBT Silicon Modules 配置:Dual 集電極—發(fā)射極最大電壓 VCEO:600 V 集電極—射極飽和電壓:1.95 V 在25 C的連續(xù)集電極電流:230 A 柵極—射極漏泄電流:400 nA 功率耗散:445 W 最大工作溫度:+ 125 C 封裝 / 箱體:34MM 封裝: |
| FS800R07A2E3BOSA2 | 制造商:Infineon Technologies AG 功能描述:Trans IGBT Module N-CH 650V 700A 33-Pin |
發(fā)布緊急采購，3分鐘左右您將得到回復。