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| 型號： | FS7VS-5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | HIGH-SPEED SWITCHING USE |
| 中文描述： | 高速開關(guān)使用 |
| 文件頁數(shù)： | 40/91頁 |
| 文件大小： | 488K |
| 代理商： | FS7VS-5 |
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PSD935G2
PSD9XX Family
39
The
PSD935G2
Functional
Blocks
(cont.)
9.3.3 Microcontroller Interface Examples
Figures 15 through 19 show examples of the basic connections between the PSD935G2
and some popular microcontrollers. The PSD935G2 Control input pins are labeled as to
the microcontroller function for which they are configured. The MCU interface is specified
using the PSDsoft.
9.3.3.1 80C31
Figure 15 shows the interface to the 80C31, which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller control
signals PSEN, RD, and WR may be used for accessing the internal memory components
and I/O Ports. The ALE input (pin PD0) latches the address.
9.3.3.2 80C251
The Intel 80C251 microcontroller features a user-configurable bus interface with four
possible bus configurations, as shown in Table 15.
Configuration 1 is 80C31 compatible, and the bus interface to the PSD935G2 is identical to
that shown in Figure 15. Configurations 2 and 3 have the same bus connection as shown
in Figure 16. There is only one read input (PSEN) connected to the Cntl1 pin on the
PSD935G2. The A16 connection to the PA0 pin allows for a larger address input to the
PSD935G2. Configuration 4 is shown in Figure 17. The RD signal is connected to Cntl1
and the PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In
Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in
every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus
cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0]
are changing. The PSD935G2 supports both modes. In Page Mode, the PSD bus timing
is identical to Non-Page Mode except the address hold time and setup time with respect
to ALE is not required. The PSD access time is measured from address A[7:0] valid to
data in valid.
相關(guān)PDF資料 |
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| PSD935F3V-15B81 | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935F3V-15B81I | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 30000uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-0.1pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate |
| PSD935F3V-15J | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935F3V-15JI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD935F3V-15M | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
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