參數(shù)資料
型號(hào)： FS7VS-5
廠商： Mitsubishi Electric Corporation
英文描述： HIGH-SPEED SWITCHING USE
中文描述： 高速開(kāi)關(guān)使用
文件頁(yè)數(shù)： 78/91頁(yè)
文件大?。?/td> 488K
代理商： FS7VS-5
PSD935G2
PSD9XX Family
-90
-12
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVDV
ALE Access Time from
Power Down
128
135
ns
Maximum Delay from APD Enable
to Internal PDN Valid Signal
t
CLWH
Using CLKIN Input
15
*
t
CLCL
(μs) (Note 1)
μs
Power Down Timing
(3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
NLNH
Warm RESET Active Low Time (Note 1)
300
ns
t
OPR
RESET High to Operational Device
300
ns
t
NLNH-PO
Power On Reset Active Low Time
1
ms
Warm RESETActive Low Time
(Note 2)
t
NLNH-A
25
μs
Reset Pin Timing
(3.0 V to 3.6 V Versions)
NOTE:
1. t
CLCL
is the CLKIN clock period.
Microcontroller Interface – PSD935G2AC/DC Parameters
(3.0 V to 3.6 V Versions)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
t
BVBH
VstbyDetection to VstbyonOutput
High
(Note 1)
20
μs
t
BXBL
VstbyOff Detection to Vstbyon
Output Low
(Note 1)
20
μs
V
stbyon
Timing
(3.0 V to 3.6 V Versions)
NOTE:
1. RESET will not abort Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle.
NOTE:
1. Vstbyon is measured at V
CC
ramp rate of 2 ms.
77
相關(guān)PDF資料
PDF描述
PSD935F3V-15B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15B81I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 30000uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-0.1pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
PSD935F3V-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15M Configurable Memory System on a Chip for 8-Bit Microcontrollers
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