參數(shù)資料
型號(hào)： FS7VS-5
廠商： Mitsubishi Electric Corporation
英文描述： HIGH-SPEED SWITCHING USE
中文描述： 高速開(kāi)關(guān)使用
文件頁(yè)數(shù)： 71/91頁(yè)
文件大?。?/td> 488K
代理商： FS7VS-5
PSD9XX Family
PSD935G2
70
-70
-90
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
ALE or AS Pulse Width
15
20
Address Setup Time
(Note 1)
4
6
ns
Address Hold Time
(Note 1)
7
8
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
8
15
ns
t
SLWL
t
DVWH
t
WHDX
t
WLWH
CS Valid to Leading Edge of WR
(Note 3)
12
15
ns
WR Data Setup Time
(Note 3)
25
35
ns
WR Data Hold Time
(Note 3)
4
5
ns
WR Pulse Width
(Note 3)
28
35
ns
t
WHAX1
Trailing Edge of WR to Address
Invalid
(Note 3)
6
8
ns
t
WHAX2
Trailing Edge of WR to DPLD
Address Input Invalid
(Note 3 and 4)
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
27
30
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note 2)
20
25
ns
Write Timing
(5 V ± 10% Versions)
NOTES:
1.
Any input used to select an internal PSD935G2 function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
WR timing has the same timing as E, DS signals.
t
WHAX2
is Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
2.
3.
4.
Microcontroller Interface – PSD935G2 AC/DC Parameters
(5V ±10% Versions)
-70
-90
Slew
Rate
(Note 1)
TURBO
OFF
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
PD
PLD Input Pin/Feedback to
PLD Combinatorial Output
20
25
Add 12
Sub 2
ns
t
ARD
PLD Array Delay
11
16
ns
PLD Combinatorial Timing
(5 V ± 10%)
NOTE:
1. Fast Slew Rate output available on Port C and F.
相關(guān)PDF資料
PDF描述
PSD935F3V-15B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15B81I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 30000uF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-0.1pF; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: S Failure Rate
PSD935F3V-15J Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
PSD935F3V-15M Configurable Memory System on a Chip for 8-Bit Microcontrollers
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