參數(shù)資料
型號: GS9092-CNE3
廠商: Gennum Corporation
英文描述: GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述: GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁數(shù): 20/58頁
文件大?。?/td> 608K
代理商: GS9092-CNE3
GS9092 Data Sheet
28202 - 2
September 2005
20 of 58
The provided programmable multi-function I/O pins may be configured to input and
output various status signals including H, V, and F timing, a FIFO_FULL, and a
FIFO_EMPTY pulse. The internal FIFO supports 4 modes of operation, which may
be used for data delay, MPEG packet insertion, or ancillary data insertion.
Finally, the GS9092 contains a JTAG interface for boundary scan test
implementations.
3.2 Parallel Data Inputs
Data inputs enter the device on the rising edge of either PCLK or WR_CLK,
depending on the configuration of the internal FIFO.
When the internal FIFO is bypassed or in ancillary data insertion mode (see
Ancillary Data Insertion Mode on page 28
), data enters the device on the rising
edge of PCLK as shown in
Figure 3-1
. When the internal FIFO is configured for
video mode, data enters the device on the rising edge of WR_CLK (see
Video
Mode on page 23
).
The input data format is defined by the setting of the external SMPTE_BYPASS
and DVB_ASI pins (
Table 3-1
). Input data must be presented in 10-bit format.
Figure 3-1: PCLK to Input Data Timing
NOTE: For a SMPTE compliant serial output, the jitter on the input PCLK across
the frequency spectrum should not exceed 350ps.
CONTROL
SIGNAL INPUT
DIN[9:0]
PCLK
50%
t
IH
t
SU
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
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