參數(shù)資料
型號: GS9092-CNE3
廠商: Gennum Corporation
英文描述: GS9092 GenLINX-R III 270Mb/s Serializer for SDI and DVB-ASI
中文描述: GS9092 GenLINX - R的第三270Mb / s的串行SDI和DVB - ASI在內(nèi)
文件頁數(shù): 31/58頁
文件大?。?/td> 608K
代理商: GS9092-CNE3
GS9092 Data Sheet
28202 - 2
September 2005
31 of 58
Figure 3-7: Ancillary Data Insertion
%%
ANC_DATA_SWITCH = HIGH
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written
to second half of FIFO starting at adress zero. Application layer continues to
read from the first half of the FIFO.
Application layer
read pointer
Internal write
pointer
0
1023
1023
0
Application layer
read pointer
Internal write
pointer
0
0
1023
1023
ANC_DATA_SWITCH = LOW
0
1023
Internal write
pointer
Application layer
read pointer
ANC_DATA_SWITCH = HIGH
0
1023
ANC_DATA_SWITCH bit is toggled HIGH. New ancillary data is written to first half of
FIFO starting at address zero. Application layer continues to read from second half
of FIFO. Toggling ANC_DATA_SWITCH back LOW will clear the second half of the
FIFO and go back the situation depicted in box A.
Application layer
read pointer
Internal write
pointer
%%
0
ANC_DATA_SWITCH = LOW
1023
0
1023
ANC_DATA_SWITCH toggled LOW. First half of FIFO cleared and ancillary
data read from second half of FIFO. Device continues to write ancillary data
to second half of FIFO.
A
B
C
D
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
ANC_DATA
NOTE: At least 1100 PCLK cycles must pass between toggles of the ANC_DATA_SWITCH bit.
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