參數(shù)資料
型號： HC05JB4GRS
英文描述： 68HC(7)05JB4 General Release Specification
中文描述： 68HC（7）05JB4總發(fā)行規(guī)格
文件頁數(shù)： 13/106頁
文件大?。?/td> 1366K
代理商： HC05JB4GRS
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
GENERAL DESCRIPTION
MOTOROLA
1-3
Figure 1-1. MC68HC05J5A Block Diagram
OSCILLATOR
AND DIVIDE
BY 2
OSC1
128 BYTES
RAM
2560 BYTES
ROM
PA0
x
PA1
x
PA2
x
PA3
x
PA4
y
PA5
y
PA6
z
PA7
{
DATA
DIR
REG
PORT
A
REG
IRQ
VDD
VSS
STK PTR
COND CODE REG 1 1 1
I N Z C
H
INDEX REG
CPU CONTROL
0 0 0
1
1
0
0
0
0
0
ALU
68HC05 CPU
ACCUM
PROGRAM COUNTER
CPU REGISERS
OSC2/R
RESET
CORE
TIMER
(COP)
LOW
VOLTAGE
RESET
PB0
|
PB1
}
PB2
}~
PB3
~
PB4
~
PB5
~
DATA
DIR
REG
PORT
B
REG
y
: 8 mA current sink
z
: Open-drained with internal pull-up and
8 mA current sink
{
: External interrupt capability, open-drained
with internal pull-up and 8 mA current sink
|
: Shared pin: PB0/TCAP
}
: 25 mA current sink open-drained with
internal pull-up
x
: External edge interrupt capability
~
: not bonded out in 16-pin package
16-BIT
TIMER
TCAP
|
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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