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參數(shù)資料
| 型號： | HC05JB4GRS |
| 英文描述： | 68HC(7)05JB4 General Release Specification |
| 中文描述： | 68HC（7）05JB4總發(fā)行規(guī)格 |
| 文件頁數(shù)： | 67/106頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | HC05JB4GRS |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
16-BIT TIMER
MOTOROLA
9-9
IEDG - INPUT CAPTURE EDGE SELECT
The state of this read/write bit determines whether a positive or negative transi-
tion on the TCAP pin triggers a transfer of the contents of the timer register to
the input capture register. Reset has no effect on the IEDG bit.
1 =
Positive edge (low to high transition) triggers input capture.
0 =
Negative edge (high to low transition) triggers input capture.
9.5
TIMER1 STATUS REGISTER (T1SR)
The timer status register (T1SR) shown in
Figure 9-12
contains flags for the fol-
lowing events:
An active signal on the PB0/TCAP pin, transferring the contents of the
timer registers to the input capture registers.
An overflow of the timer registers from $FFFF to $0000.
Writing to any of the bits in the T1SR has no effect. Reset does not change the
state of any of the flag bits in the T1SR.
ICF - INPUT CAPTURE FLAG
The ICF bit is automatically set when an edge of the selected polarity occurs on
the PB0/TCAP pin. Clear the ICF bit by reading the timer status register with
the ICF set, and then reading the low byte (ICL, $0015) of the input capture
registers. Reset has no effect on ICF.
T1OF - TIMER1 OVERFLOW FLAG
The T1OF bit is automatically set when the 16-bit timer counter rolls over from
$FFFF to $0000. Clear the T1OF bit by reading the timer status register with
the T1OF set, and then accessing the low byte (TCNTL, $0019) of the timer
registers. Reset has no effect on T1OF.
9.6
TIMER1 OPERATION DURING WAIT MODE
During WAIT mode the 16-bit timer continues to operate normally and may gener-
ate an interrupt to trigger the MCU out of the WAIT mode.
9.7
TIMER1 OPERATION DURING STOP MODE
When the MCU enters the STOP mode the free-running counter stops counting
(the internal processor clock is stopped). It remains at that particular count value
until the STOP mode is exited by applying a low signal to the IRQ pin, at which
BIT 7
ICF
BIT 6
0
BIT 5
T1OF
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
T1SR
$0013
R
W
reset:
U
U
U
0
0
0
0
0
U = UNAFFECTED BY RESET
Figure 9-12. Timer Status Registers (T1SR)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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